Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-14
2005-06-14
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06907596
ABSTRACT:
A mask data generating apparatus comprising: a division module configured to extract a line segment and dividing the extracted line segment into a suitable length; a correction value calculation module configured to calculate correction value calculating points from each divided edge; a first calculated center point calculation module configured to set first calculated center points and a shape of a pattern; a first rectangular region preparation module configured to prepare first simulation regions and a plurality of first rectangular regions which overlap with each other; a second calculated center point calculation module configured to acquire second rectangular regions, and calculating second calculated center points based on the second rectangular regions; a second simulation region preparation module configured to acquire second simulation regions; a process simulation execution module configured to calculate a correction value; and a correction pattern preparation module configured to prepare the correction pattern.
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Kobayashi Sachiko
Kotani Toshiya
Tanaka Satoshi
Watanabe Susumu
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Levin Naum
Siek Vuthe
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