Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-10-24
2004-04-06
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
C438S017000, C438S018000
Reexamination Certificate
active
06716653
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a structure for measuring mask and layer alignment in semiconductor fabrication processes.
BACKGROUND OF THE INVENTION
Modern integrated circuits (ICs) are fabricated in multiple layers on a silicon wafer, each layer representing a 2-dimensional layout of device elements (e.g., gates, gate dielectrics, source/drain regions, etc.). Typically, photolithographic techniques are used to produce the patterns for each layer, with those patterns controlling the subsequent formation of the device elements in a particular layer. To ensure proper function of an IC, the multiple layers making up that IC must be precisely aligned, meaning that the associated masks used in the photolithographic process steps must be aligned. It is therefore important to be able to monitor and measure this mask or layer alignment.
A common method for mask alignment involves target markings on the masks and wafers. Through the use of high-magnification equipment or similar optical sensing techniques, misalignment can be visually measured and monitored. However, this manual technique is time-consuming and susceptible to human error. Consequently, such a technique is not feasible for gathering a large statistical base of information or monitoring a relatively large number of wafers.
To overcome the aforementioned limitations of manual measurement techniques, electrical test methods have been developed. Conventional electrical alignment test methods involve the creation of special multi-layer conductive elements using the same fabrication processes being used to produce the actual ICs. The multi-layer conductive elements are configured such that any misalignment between layers results in a change in the resistance of the conductive elements. By comparing the measured resistance with a baseline (i.e., no misalignment) resistance value, the total amount of misalignment between layers can be determined.
FIG. 1
shows an example of a conventional electrical alignment test structure
100
, as described in U.S. Pat. No. 4,571,538, issued Feb. 18, 1986 to Chow. Test structure
100
comprises a plurality of u-shaped features
130
, a plurality of rectangular features
120
, a plurality of square features
110
, and contact pads A, B, and C. The plurality of u-shaped features
130
are formed in a polysilicon layer. The pattern of square features
110
is formed in a contact layer. Finally, the pattern of rectangular features
120
and pads A, B, and C are formed in a metal layer.
To form test structure
100
, the plurality of u-shaped features
130
are formed in the polysilicon layer during the same process steps used to form other polysilicon layer features in the IC. Next, the plurality of square features
110
are formed during a contact process step, and the plurality of rectangular features
120
, and pads A, B, and C are formed during a metallization process step. A dielectric layer (not shown) isolates the plurality of u-shaped features
130
from the plurality of rectangular features
120
. Therefore, the plurality of square features
110
provide the only electrical contact between the u-shaped features
130
and the rectangular features
120
.
Test structure
100
enables measurement of any misalignment between the polysilicon layer (features
130
) and the contact layer (features
110
) in the Y-direction (as indicated by the axes in FIG.
1
). If the contact layer and polysilicon layers are perfectly aligned, the electrical paths between pads A and C and pads B and C are substantially the same length, and therefore the resistances between pads A and C (Rac) and between pads B and C (Rbc) are substantially the same. However, if the contact layer is shifted in the positive Y-direction (upwards) with respect to the polysilicon layer, the electrical path between pads A and C becomes longer than the path between pads B and C, and therefore resistance Rac becomes greater than resistance Rbc. Likewise, if the contact layer is shifted in the negative Y-direction (downwards) with respect to the polysilicon layer, resistance Rac becomes less than resistance Rbc. In this manner, the Y-direction alignment of the polysilicon and contact layers (and masks) can be measured. A second test structure can be oriented perpendicular to test structure
100
to provide X-axis alignment measurement.
FIG. 2
shows another example of a conventional alignment test structure
200
, as described in U.S. Pat. No. 4,386,459, issued Jun. 7, 1983 to Boulin. Test structure
200
comprises a serpentine conductive member
210
, contact pads A-I, and contacts Ca—Ci. Conductive member
210
comprises contiguous linear elements
211
-
220
forming two interconnected S-shaped elements in a first layer, such as a metal, polysilicon, or diffusion layer. The first S-shaped element comprises horizontal elements
211
,
213
, and
215
, and vertical elements
212
and
214
. The second S-shaped element comprises vertical elements
216
,
218
, and
220
, and horizontal elements
217
and
219
. Contact pads A-I are formed in a second layer, such as a metal layer, that overlies an insulating layer (not shown) on the first layer. Contacts Ca—Ci are formed in a third layer between the first and second layers, providing electrical contact between contact pads A-I and conductive member
210
.
Contact pads A-I are located along conductive member
210
such that when the first and second layers are properly aligned, the electrical path from pad B to pad C (Pbc) is the same length as the electrical path from pad C to pad D (Pcd), and the electrical path from pad F to pad G (Pfg) is the same length as the electrical path from pad G to pad H (Pgh). Under such circumstances, the resistances between pads B and C (Rbc) and pads C and D (Rcd) would be the same, as would the resistances between pads F and G (Rfg) and pads G and H (Rgh). Misalignment between the first and second layers would change the relative lengths of the electrical paths described above, thereby creating resistance differentials indicative of the misalignment. For example, if the second mask (contact pads A-I) is shifted in the positive Y-direction with respect to the first mask (conductive element
210
), the length of electrical path Pfg is reduced, while the length of electrical path Pgh is increased. Consequently, resistance Rfg becomes smaller than resistance Rgh, and a positive Y-axis misalignment is indicated. Similarly, if the second mask is shifted in the positive X-direction with respect to the first mask, the lengths of electrical paths Pbc and Pcd are decreased and increased, respectively. Therefore, resistance Rbc becomes smaller than resistance Rcd, thereby indicating a positive X-axis misalignment.
FIG. 3
a
shows another example of a conventional alignment test structure
300
, as described in U.S. Pat. No. 5,770,995, issued Jun. 23, 1998 to Kamiya. Test structure
300
comprises two conductive regions
310
in a first layer, four triangular openings
320
in a second layer formed over the first layer, and contact pads A and B and an interconnect
330
in a third layer formed over the second layer. The four triangular openings
320
are arranged linearly, with two triangular openings
320
being formed over one of the conductive regions
310
, and the other two triangular openings
320
being formed over the other conductive region
310
. Contact pad A extends over one of the outer triangular openings
320
, while contact pad B extends over the other outer triangular opening
320
, with interconnect
330
being formed over the two inner triangular openings
320
.
As shown in cross-section S—S of
FIG. 3
b
, contact pads A and B and interconnect
330
(third layer) are insulated from conductive regions
310
(first layer) by a dielectric layer
350
(second layer). However, electrical contact is made between the first and third layers where contact pads A and B and interconnect
330
extend through triangular openings
320
to meet conductive regions
310
. A contact layer can be included under pads A and B and interconnect
Hsueh Shih-Cheng
Look Kevin T.
Harms Jeanette S.
Jr. Carl Whitehead
Schillinger Laura M
Xilinx , Inc.
Young Edel M.
LandOfFree
Mask alignment structure for IC layers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Mask alignment structure for IC layers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mask alignment structure for IC layers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3250103