Marginless status determination circuit

Details Marginless status determination circuit Marginless status determination circuit

2005-09-30

2008-11-18

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C714S699000, C714S700000

Reexamination Certificate

active

07454649

ABSTRACT:
By including a unit for storing data to be determined, a unit for delaying the data, a unit for storing the output of the delay unit, and a unit for comparing the storage contents of the data before the delay with the storage contents of the data after the delay, and outputting a marginless status detection signal when they are different, the presence/absence of a margin is monitored regardless of ambient conditions by using an output marginless status detection signal as a switch control signal for a clock switch circuit, thereby operating electronic equipment without changing a frequency of a clock signal up to the critical condition.

REFERENCES:
patent: 5870404 (1999-02-01), Ferraiolo et al.
patent: 6178332 (2001-01-01), Norman et al.
patent: 6247138 (2001-06-01), Tamura et al.
patent: 6249445 (2001-06-01), Sugasawa
patent: 2001/0013111 (2001-08-01), Bishop et al.
patent: 3-251912 (1991-11-01), None

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