Mapping logical cache indexes to physical cache indexes to reduc

Details Mapping logical cache indexes to physical cache indexes to reduc Mapping logical cache indexes to physical cache indexes to reduc

1998-02-11

2000-09-05

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711134, 711206, G06F 1210

Patent

active

061157937

ABSTRACT:
A cache memory system which minimizes the latency and latency uncertainty of data memory access by allocating spare cache memories to subsequent conflicting requests, and maintaining the prior requests in a separate table until the prior request is satisfied and the prior allocated cache is free. This reallocation of physical caches to conflicting requests is effected by maintaining an index to the physical cache that is separate and distinct from the logical index associated with the requests that cause the conflict. A conventional indexed cache mechanism is employed to derive the logical index from a subset of the address of the requested data. When the same logical index occurs from data requests from different blocks of memory, the conflict is resolved by assigning a free physical cache to the latter request. The latter assignment is stored in the indexed cache table, and the former assignment is stored in a separate table until it is no longer required.

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patent: 5752261 (1998-05-01), Cochcroft, Jr.
patent: 6049849 (2000-04-01), Arimilli et al.

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