Mapping heterogeneous logic elements in a programmable logic...

Details Mapping heterogeneous logic elements in a programmable logic... Mapping heterogeneous logic elements in a programmable logic...

1998-10-09

2001-02-27

Teska, Kevin J. (Department: 2768)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06195788

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to methods for fitting logic functions in an integrated circuit. More specifically, the invention relates to performing the fitting function using heterogeneous logic elements.
During the design phase of a new electronic product (e.g., an integrated circuit), logic functions must be designed, tested, and ultimately laid-out on a substrate (e.g., silicon or other semiconductor). The layout component of this process typically involves mapping hardware independent logic cells onto elementary units of hardware to form logic elements. Subsequent steps involve placement of these logic elements onto specified locations on the substrate and routing lines between the various logic blocks on the substrate. These functions are generically referred to as “place and route.”
In some electronic products—notably some programmable logic devices—the layout of logic on the substrate assumes a hierarchy. In this hierarchy, fundamental units of logic may be referred to as logic cells or logic elements. These logic cells may be grouped into larger blocks of logic that may be referred to as “logic array blocks” for example. These blocks of logic may, in turn, be grouped into rows and ultimately columns on the hardware device.
Modern tools for designing electronic products are implemented as software. This software may allow the designer to specify the desired functioning of the end device, as well as some architectural and logic constraints. The software tools can take this information and, with the designer's aid, develop Boolean, schematic, and ultimately hardware designs. In the design process, the software fits the logic onto the hardware device to provide the final design layout.
Typically the design software “compiles” a design to produce a hardware layout. Compilation takes as an input a user's specifications (including high and low level logic constraints, timing requirements, etc.) and then synthesizes that design maps it onto elementary units of hardware, and fits it onto a target hardware device. In the case of programmable devices, the resulting compiled electronic design is then used to program a blank (unprogrammed) device. Designs for application specific integrated circuits, including programmable logic devices (PLDs) and field programmable gate arrays, as well as non-programmable electronic devices such as gate arrays all may require compilation involving synthesis of logic functions and fitting.
Normally, during PLD compilation, a user's design requirements are first synthesized to generate the gates and nets necessary to implement the design. The synthesized design is then “mapped” to a particular target hardware device. The target hardware device will have elementary units of hardware on which logic is implemented. The PLD into which the synthesized design is being mapped is typically homogeneous in that the PLD contains a single type of elementary logic unit. Such elementary logic units can include look up table (LUT) type logic devices as well as product term type (PTERM) logic devices. In the case of look-up table devices, the elementary unit may be a logic element that includes a four input look-up table together with a register. In the case of a product term device, the fundamental hardware unit is a product term or product term cell. One example of the homogeneous type PLD architecture is illustrated by the FLEX PLD architecture manufactured by the Altera Corporation of San Jose, Calif. having logic elements in the form of look up tables (LUT). However, the RAPHAEL programmable logic device also developed by the Altera Corporation contains a heterogeneous environment. In that environment, logic may be mapped to look up tables and product terms on a target hardware device In the case of the RAPHAEL architecture, speed and size considerations militate in favor of PTERM logic elements over LUT type logic cells. However, since there are typically more LUT type logic elements than PTERM logic elements, the mapping must be carried out with the view to optimize the use of the PTERM logic elements. After the logic has been mapped into PTERM and LUT logic elements, the resulting elements are fit onto the hardware device by a place and route procedure.
The mapping process is dependent upon the particular hardware architecture employed and mapping to look up table architectures is fundamentally different than mapping to product term architectures. For this reason, it is desirable to find methods and mechanisms for use in mapping heterogeneous logic elements in a programmable logic device.
SUMMARY OF THE INVENTION
The present invention provides a method and mechanism for mapping heterogeneous logic elements in a portion of electronic design compilation for a programmable integrated circuit. Specifically, the invention provides a method to perform the technology mapping of heterogeneous logic elements in a programmable logic device. In a preferred embodiment, the method performs the operations necessary to selectively map heterogeneous logic cells for use in a hierarchical electronic design. In a particularly preferred embodiment, the method selectively chooses the combination of product term logic elements and look up logic elements.
One aspect of the invention provides a method of compiling an electronic design. The method is performed by forming a first logical region using the first type logic device and forming a second logical region using the second type logic device, wherein the first logical region and the second logical regions perform logically equivalent sub-functions of the electronic design. The first logical region and the second logical regions are then compared, and then based upon the comparing, either the first or the second logical region is selected based upon a pre-determined factor. The chosen logical region is then added to a final mapping list. The method proceeds until the electronic design is fully mapped.
In a preferred embodiment of the invention, heterogeneous logic elements include PTERM logic elements and LUT logic elements.
These and other features and advantages of the present invention will be further described in the following description of the invention in conjunction with the associated figures.


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