Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2005-06-28
2005-06-28
Lane, Jack A. (Department: 2188)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S219000, C711S220000, C365S230030
Reexamination Certificate
active
06912616
ABSTRACT:
One embodiment of the invention is a memory controller that maps a received address to a memory location in a plurality of memory banks, the memory controller comprising: circuitry for calculating a remainder from a division of the received address by a divisor, wherein the divisor is based on the number of the plurality of banks; circuitry for determining a particular bank of the plurality of banks based on the remainder and at least one bit of the received address; and circuitry for determining the memory location in the particular bank using at least a portion of the received address.
REFERENCES:
patent: 5134695 (1992-07-01), Ikeda
patent: 6070227 (2000-05-01), Rokicki
patent: 6405286 (2002-06-01), Gupta et al.
patent: 2004/0064666 (2004-04-01), Bickerstaff
Patterson, David. A and John L. Hennessy, “Computer Architecture A Quantitative Approach”, 2nd Edition. Chapter 5 Memory Hierarchy Design, pp. 435-437 (1996).
Gao, Q.S. “The Chinese Remainder Theorem and the Prime Memory System,” IEEE (1993) pp. 337-340.
Hewlett--Packard Development Company, L.P.
Lane Jack A.
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