Mapping address bits to improve spread of banks

Details Mapping address bits to improve spread of banks Mapping address bits to improve spread of banks

2011-08-09

2011-08-09

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S157000, C711S202000, C711SE12058, C711SE12079

Reexamination Certificate

active

07996597

ABSTRACT:
A device may include a group of requestors issuing requests, a memory that includes a set of memory banks, and a control block. The control block may receive a request from one of the requestors, where the request includes a first address. The control block may perform a logic operation on a high order bit and a low order bit of the first address to form a second address, identify one of the memory banks based on the second address, and send the request to the identified memory bank.

REFERENCES:
patent: 5287470 (1994-02-01), Simpson
patent: 5390308 (1995-02-01), Ware et al.
patent: 5649143 (1997-07-01), Parady
patent: 6108745 (2000-08-01), Gupta et al.
patent: 6553478 (2003-04-01), Grossier
patent: 6604166 (2003-08-01), Jana et al.
patent: 7266651 (2007-09-01), Cypher
patent: 7398362 (2008-07-01), Tischler
patent: 2003/0196026 (2003-10-01), Moyer
Zhao Zhang, Zhichun Zhu, and Xiaodong Zhang. “Breaking Address Mapping Symmetry at Multi-levels of Memory Hierarchy to Reduce DRAM Row-buffer Conflicts.” 2002. Journal of Instruction-Level Parallelism. vol. 3.
Jun Shao and Brian T. Davis. “The Bit-reversal SDRAM Address Mapping.” 2005. ACM. SCOPES '05.
Wei-fen Lin, Steven K. Reinhardt, and Doug Burger. “Reducing DRAM Latencies with an Integrated Memory Hierarchy Design.” Jan. 2001. IEEE. HPCA '01.
Zhao Zhang, Zhichun Zhu, and Xiadong Zhang. “A Permutation-based Page Interleaving Scheme to Reduce Row-buffer Conflicts and Exploit Data Locality.” 2000. IEEE. MICRO 2000.
John L. Hennessy and David A. Patterson. Computer Organization and Design. 1998. Morgan Kaufmann. pp. 540-541 and 544.
Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo Hamalainen, and Jukka Saarinen. “Configurable Address Computation in a Parallel Memory Architecture.” Jul. 2001. WSEAS. CSCC 2001.
G.S. Sohi, “Logical Data Skewing Schemes for Interleaved Memories in Vector Processors”, Computer Sciences Technical Report #753, Feb. 1988, 23 pages.
J. Liedtke, “Colorable Memory”, IBM T.J. Watson Research Center, Nov. 10, 1996, 4 pages.
J.M. Frailong et al., “XOR-Schemes: A Flexible Data Organization in Parallel Memories”, 1985 International Conference on Parallel Processing, IEEE Computer Society, pp. 276-283, Aug. 1985.

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