Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step
Patent
1982-09-27
1984-05-29
Massie, Jerome W.
Adhesive bonding and miscellaneous chemical manufacture
Delaminating processes adapted for specified product
Delaminating in preparation for post processing recycling step
29578, 29591, 156657, 1566591, 156662, 156668, 357 51, 357 59, 357 67, 357 71, 430314, 430315, H01L 2122, H01L 21308
Patent
active
044513283
ABSTRACT:
A process for manufacturing high-resistance elements for integrated circuits, in which the resistors are positioned on a layer of silica covering an integrated circuit, in a polycrystalline silicon zone possessing high resistivity, current supply lines being formed of a layer of polycrystalline silicon possessing low resistivity, surmounted by a layer of tantalum silicide. Plugs of photosensitive resin, deposited on a layer of polycrystalline silicon, are used to mark out a zone where the resistor is to be positioned, from zones in which resistivity is reduced by doping, and also to "lift-off" the layer of tantalum silicide on top of the resistor position.
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patent: 4267558 (1981-05-01), Guterman
patent: 4291328 (1981-09-01), Lien et al.
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patent: 4332839 (1982-06-01), Levinstein et al.
patent: 4362597 (1982-12-01), Fraser et al.
Lloyd et al., "Polysilicon . . . Fabrication", IBM Technical Disclosure Bulletin, vol. 23, No. 7A, (12/80), pp. 2811-2812.
Rideout, "Method . . . Lines", IBM Technical Disclosure Bulletin, vol. 23, No. 6, (11/80), pp. 2563-2566.
Massie Jerome W.
Societe pour l'Etude et la Fabrication de Circuits Integres Spec
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