Manufacturing semiconductor device including forming a...

Details Manufacturing semiconductor device including forming a... Manufacturing semiconductor device including forming a...

2002-11-20

2004-10-05

Brewster, William M. (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S217000, C438S223000, C438S227000, C438S232000

Reexamination Certificate

active

06800513

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention concerns a semiconductor integrated circuit device comprising, as a main constituent element, an insulated gate field effect transistor (generally referred to as MOS transistor) capable of operating at low voltage and large current, as well as a manufacturing method thereof. Particularly, it relates to a semiconductor integrated circuit device comprising, as a main constituent element, MOS transistor of a silicon on insulator (referred to as SOI) structure and a manufacturing method thereof.
2. Description of the Related Art
A MOS transistor of an SOI structure (hereinafter referred to as SOI MOS) has generally been known as one of means for reducing the degradation of MOS transistor characteristics along with refinement. As a device structure of a further improved SOI MOS transistor, a double gate SOI MOS shown in
FIG. 2
is known and described, for example, in Japanese Patent Laid-Open 2000-208770. That is, the double gate SOI MOS is fabricated by forming a source diffusion layer
110
and a drain diffusion layer
111
in self-alignment with a dummy gate electrode in an SOI layer
105
, then forming a trench of a pattern opposite to the dummy gate electrode and forming a buried gate
200
by ion implantation from the trench to the support substrate
1
successively and then selectively burying a metal film such as of W into the trench region to form an upper gate electrode.
As MOS transistor of another SOI structure, MOS transistor of a double gate SOI structure shown in
FIG. 3
for the cross sectional structure has also been known.
FIG. 3
is an example of a complementary MOS transistor (hereinafter simply referred to as CMOS) in which the left-half shows a P-channel MOS transistor (hereinafter simply referred to as PMOS) region and the right-half shows an N-channel MOS transistor (hereinafter simply referred to as NMOS) region. In the double gate SOIMOS shown in
FIG. 3
, a device isolation insulative film
101
referred to as LOCOS, a gate insulative film
102
and gate electrodes
103
,
104
are previously formed by using a usual Si substrate and then an insulative film
100
of a relatively low softening temperature is deposited on the main surface and the surface is planarized and then bonded with a support substrate
1
.
After the wafer bonding step, grinding and chemical mechanical polishing are applied from the rear face of the Si substrate on which the device is formed, to form thin SOI layers
105
,
106
. In the chemical-mechanical-polishing, the thin SOI layers
105
,
106
are left selectively by utilizing the bottom of the device isolation insulative film
101
for stopping of polishing. From this state, after forming second gate electrodes
108
,
109
in alignment with gate electrodes
103
,
104
to the chemical mechanical polished surface of the thin SOI layers
105
,
106
and then source diffusion layers
110
,
113
and drain diffusion layers
111
,
112
are formed in self-alignment with second gate electrodes
108
,
109
according to the known MOS manufacturing technique. In
FIG. 3
, those portions after the metallization step are omitted for the simplification of explanation.
The double gate SOIMOS has features such as high speed operation characteristics based on low junction parasitic capacitance, complete avoidance of latch-up failure based on complete device isolation, radiation hardness characteristics. Further, since the entire SOI layer functions as a channel by upper and lower gate electrodes, it has a feature capable of minimizing the cut-off current and maximizing the conduction current.
A technique of forming the upper electrode and the buried gate electrode disposed therebelow (impurity layer at high concentration) in self-alignment is disclosed in Japanese Patent Laid-Open No. 2000-208770, which can solve the problem of the pattern shift caused by the bonding method of the prior art. However, no consideration has been taken for increasing the concentration of the impurity sufficiently high at the boundary relative to the buried gate insulative film thereby preventing depletion in the buried gate layer.
Further, in either the bonding method or the oxygen ion implantation method in the double gate SOIMOS of forming by the wafer bonding technique described above, (100) face is usually used for the SOI substrate. This is because the planarity at the bonded boundary is favorable in the former, while the defect recovery characteristics are favorable in the latter. When vertical ion implantation is applied to a support substrate comprising the (100) face by way of the reversed gate pattern trench as shown in
FIG. 2
, it is extremely difficult to avoid the channeling phenomenon well-known in the implantation method. Implanted ions reach as far as several times a predetermined depth to be reached by the channeling phenomenon to bring about problems of necessary extension of the distribution for the impurity concentration and lowering of the maximum impurity concentration.
Further, in the wafer bonding technique described above, a heat treatment at a temperature of 900° C. or higher is required as a heat treatment after bonding for ensuring adhesion strength after bonding and, usually, a heat treatment at 1100° C. has been adopted. Because of stresses in the wafer bonding step, not uniform pattern shift is caused in the wafer to bring about a problem of making it sometimes impossible for aligning between the lower gate electrodes
103
,
104
and the upper gate electrodes
108
,
109
. Further, in the bonding technique described above, use of the bonding surface as the gate insulative film involves a problem in view of reliability and it has been difficult to reduce the thickness of the SOI film or the buried gate insulative film.
Further, a well structure is generally used for the isolation in the substrate but formation of the well structure on every MOS unit results in increase of occupation area and increase of parasitic capacitance, contrary to the improvement of the performance of MOS. Meanwhile, in the known SOIMOS technique, while an oxide film isolation structure is used instead of the well structure, for example, as described in Japanese Patent Laid-Open Hei 8-130315, it involves a problem that the buried gate electrodes can not be completely isolated electrically from each other.
This invention intends to provide a high performance super-fine double gate SOIMOS in which an impurity is re-distributed at a high concentration on the boundary of a buried gate insulative film and double gates are positioned in a self-alignment manner, and the buried gate electrodes are completely isolated electrically from each other, as well as a manufacturing method thereof.
SUMMARY OF THE INVENTION
This invention is attained by:
(1) a method of manufacturing a semiconductor integrated circuit device comprising;
preparing a wafer in which a first semiconductor layer comprising an amorphous semiconductor or polycrystalline semiconductor, a first insulative film and a second semiconductor area are stacked in this order,
forming a second insulative film to a partial region on the main surface of the second semiconductor layer of the wafer including a region to form a gate electrode,
forming an impurity layer at high concentration to a region in the first semiconductor layer opposing to the region to form the gate electrode,
forming a third insulative film on the second semiconductor layer to the region to form the gate electrode and
disposing an upper gate electrode to the region to form the gate electrode on the side of the main surface of the second semiconductor layer by way of the third insulative film;
(2) a method of manufacturing a semiconductor integrated circuit device according to (1) above wherein the impurity layer at high concentration is formed by implanting a desired impurity ions passing through the second insulative layer, the second semiconductor layer and the first insulative layer into the first semiconductor layer to obtain a maximum impurity concentration in the

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