Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
1999-12-07
2003-04-01
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S197000, C438S222000
Reexamination Certificate
active
06541318
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing process of a high integration density power MOS device. Particularly, the invention relates to a manufacturing process of a low voltage power MOS device, with a perfect level surface and plain junctions.
2. Discussion of the Related Art
A known class of low voltage power MOS devices is constituted by devices obtained in EHD (Extremely High Density) technology of the type described, for example, in the European patent application EP 0772242 in the name of the same applicant. Referring to
FIG. 1
, a cross-section view of an EHD power MOS device is shown. A N+ type semiconductor substrate
1
and a N− type semiconductor layer
2
epitaxially grown over the N+ substrate
1
constitute the MOS device drain.
Inside the drain region, particularly in the N− layer
2
, diffused P type regions
3
are obtained which constitute the device body regions. In the body regions
3
there are N+ regions
5
which form the device source. Also the source regions
5
are diffused regions.
Over the upper surface of the device there are gate electrodes formed by a thin gate oxide layer
8
, a polysilicon layer
9
superimposed on the gate oxide layer
8
, and finally an insulating dielectric layer
10
located over the polysilicon layer
9
. At the sidewalls of the gate electrodes there are oxide spacers
12
for electrically insulating the gate.
As a consequence of a thermal process, the body regions
3
diffuse under the gate electrode, and in this areas, indicated with
4
in
FIG. 1
, a channel will form due to the MOS effect in the N− semiconductor layer
2
between the source regions
5
and the drain region, indicated with
6
.
The source regions
5
and the body regions
3
are formed in aligned way to the polysilicon regions
9
which form the gate electrode. On the outer part of the device and obtained in the semiconductor layer
2
, there are diffused P type regions
7
which have the function to electrically connect all the body regions
3
that are on the device boundary.
Moreover, the device includes a metal layer
11
over the upper surface, suitable to connect the source regions
5
and the body regions
3
, and a metal layer
13
on the lower surface of the N+ semiconductor substrate
1
, for the drain electrode connection.
FIG. 1
shows also a field oxide region
14
which delimits the device active area.
For obtaining such a structure, a process providing at least six photolithographic steps is necessary.
Moreover, the conduction resistance Ron of the device has a non negligible component due to the JFET effect (R
JFET
), because there are body regions
3
placed in front of each other that form depletion regions which reduce the drain regions
6
, increasing their resistance.
Other MOS structures exist having recessed gate with a variously shaped trench on the epitaxial layer. These structures are obtained over a semiconductor substrate using a non isotropic etching of the substrate itself for forming the trenches with a proper slope. Over each one of the two sides of the resulting trench, a conductive channel will form.
In view of the state of the art described, it is an object of the present invention to provide a process of manufacturing a high integration density power MOS device with reduced conduction resistance Ron.
SUMMARY OF THE INVENTION
According to the present invention, these and other objects are achieved by a process of manufacturing a semiconductor device comprising a step of forming recessed zones in a semiconductor layer of a first conductivity type, a step of oxidation for forming a gate oxide layer at the sidewalls of said recessed zones, a step of forming a polysilicon gate electrode inside said recessed zones, a step of forming body regions of a second conductivity type in said semiconductor layer between said recessed zones, and a step of forming source regions of the first conductivity type in said body regions, wherein said step of forming recessed zones comprises a step of local oxidation (LOCOS) of the surface of said semiconductor layer wherein said recessed zones will be formed, with an oxide growth on and into said semiconductor layer in order to obtain thick oxide regions penetrating in said semiconductor layer, and a step of etching wherein the oxide of said thick oxide regions is removed.
REFERENCES:
patent: 4599789 (1986-07-01), Gasner
patent: 4710265 (1987-12-01), Hotta
patent: 5212100 (1993-05-01), Groves et al.
patent: 5723376 (1998-03-01), Takeuchi et al.
patent: 5827764 (1998-10-01), Liaw et al.
patent: 5915180 (1999-06-01), Hara et al.
patent: 5958505 (1999-09-01), Mantl
patent: A-44 15 412 (1994-05-01), None
patent: WO-A-98/04004 (1998-01-01), None
European Search Report from European Patent Application 98830738.5, filed Dec. 9, 1998.
Patent Abstracts of Japan, vol. 017, No. 006 (E-1302), Jan. 7, 1993 & JP-A-04 239778 (Fuji Electric Co. Ltd.).
Patent Abstracts of Japan, vol. 005, No. 167 (E-079), Oct. 24, 1981 & JP-A-56 096865 (Fujitsu Ltd.).
Patent Abstracts of Japan, vol. 009, No. 075 (E-306, Apr. 4, 1985 & JP-A-59 211276 (Toshiba KK).
Rocchegiani Renzo N.
Smith Matthew
STMicroelectronics S.R.L.
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