Manufacturing process for semiconductor integrated circuits

Details Manufacturing process for semiconductor integrated circuits Manufacturing process for semiconductor integrated circuits

1984-10-17

1986-01-28

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29571, 29576W, 29580, 148187, 156646, 156648, 156653, 156656, 156657, 1566611, 156662, 357 42, 357 71, 427 38, 427 90, 427 93, H01L 21306, B44C 122, C03C 1500, C23F 102

Patent

active

045669406

ABSTRACT:
A semiconductor integrated circuit in which layers such as an field isolation region, a gate electrode, interlayer insulating films and interconnection lines are formed by the combined use of a lift-off process and an ECR plasma deposition process. According to the present invention, even if vertical dimensions of patterns of the respective layers are large as compared with their lateral dimensions, the upper surfaces of the respective layers can be planarized, permitting the fabrication of an LSI of high packing density, high operating speed and high reliability which is free from shorting and breakage of the interconnection lines.

REFERENCES:
patent: 4300279 (1981-11-01), Wieder
patent: 4367119 (1983-01-01), Logan et al.
patent: 4381595 (1983-05-01), Denda et al.
patent: 4389481 (1983-06-01), Poleshuk et al.

Affiliated with

Also associated with

Rating

Manufacturing process for semiconductor integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Manufacturing process for semiconductor integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacturing process for semiconductor integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1304837