Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-28
2003-12-30
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06671861
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-095968, filed Mar. 29, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing process evaluation method for a semiconductor device and a pattern shape evaluation apparatus using the method, which evaluate a pattern misalignment between layers in the semiconductor device.
2. Description of the Related Art
In a semiconductor product, the degree of overlapping between patterns on layers need meet a certain requirement for the purpose of electric conduction between a wiring pattern on a given layer and a pattern on an overlapping adjacent layer. In the prior art, the amount of displacement in the overlapping (hereinafter referred to as “misalignment”) is quantized and managed.
A description will now be given of a prior-art method of evaluating a pattern misalignment between layers of a semiconductor device.
In general, the amount of misalignment is measured using a purpose-specific pattern.
FIGS. 11A and 11B
are plan views showing configurations of misalignment measurement patterns.
FIG. 11B
is an enlarged view of part of FIG.
11
A.
As is shown in
FIG. 11A
, patterns
1
and
2
are formed on a first layer, and patterns
3
and
4
are formed on a second layer provided on the first layer. As is shown in
FIG. 11B
, a distance between a middle point
5
, which lies between the patterns
1
, and a middle point
6
, which lies between the patterns
3
, is measured as a horizontal misalignment amount
7
. Similarly, a distance between a middle point
8
, which lies between the patterns
2
, and a middle point
9
, which lies between the patterns
4
, is measured as a vertical misalignment amount
10
.
As is shown in
FIG. 12
, when misalignment of patterns of an actual product is to be evaluated, an image of a scanning electron microscope (SEM) is obtained from just above the patterns
11
. Dimensions
13
and
14
of patterns
12
formed on a first layer, which are partly visible under the patterns
11
formed on a second layer, are measured, and the misalignment is effected.
With modern progress in miniaturization of semiconductor devices, even if the amount of misalignment measured in design pattern data (CAD data) using a purpose-specific pattern is within a tolerable range, actual manufacture may not be carried out according to design dimensions due to reduction at a pattern end(shortening), etc. Consequently, observation of patterns of an actual product becomes necessary. In this case, it is necessary, as a minimum requirement, to form a plurality of patterns to be observed, and locations for measurement may vary depending on pattern layouts. Thus, the measurement of dimensions is complex and time-consuming.
As has been described above, with modern miniaturization of patterns, actual patterns formed by exposure may considerably differ from design dimensions. This necessitates a test for misalignment using the actual produced patterns. A plurality of pattern layers to be inspected need to be formed as a minimum requirement, and locations of measurement may vary, depending on pattern layouts.
BRIEF SUMMARY OF THE INVENTION
(1) According to an aspect of the present invention, there is provided a semiconductor device manufacturing process evaluation method comprising: acquiring first wiring pattern data corresponding to a shape of a wiring pattern on a layer in a semiconductor device, on the basis of a first image obtained by imaging a sample which permits imaging of the wiring pattern; generating evaluation CAD data which synthesizes CAD data of a plurality of layers, which includes wiring CAD data of the layer with the wiring pattern; making position coordinates of the first wiring pattern data coincide with position coordinates of a wiring pattern contained in the wiring CAD data, and producing synthesis data by synthesizing the first wiring pattern data and the evaluation CAD data; and quantizing, based on the synthesis data, a degree of overlapping between the first wiring pattern data and a pattern in the CAD data of a layer other than the layer with the wiring pattern.
(2) According to another aspect of the invention, there is provided a pattern shape evaluating apparatus comprising: a database that stores CAD data of a plurality of layers, which includes first wiring pattern data corresponding to a shape of a wiring pattern on a layer in a semiconductor device and acquired on the basis of a first image obtained by imaging a sample which permits imaging of the wiring pattern, and CAD data of the layer with the imaged wiring pattern; an evaluation CAD data generating section which generates evaluation CAD data by synthesizing the CAD data of the layer with the wiring pattern and CAD data of a layer other than the layer with the wiring pattern, which are contained in the CAD data of the plurality of layers; a pattern matching section which produces synthesis data by making position coordinates of the first wiring pattern data coincide with position coordinates of a wiring pattern contained in the wiring CAD data in the evaluation CAD data, and synthesizing the first wiring pattern data and the evaluation CAD data; and a shape evaluation section which quantizes, based on the synthesis data, a degree of overlapping between the first wiring pattern data and the pattern in the wiring CAD data.
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Niewczas et al., “An Algorithm for Determining Repetitive Patterns in Very Large IC Layouts,” IEEE, Apr. 1999, pp. 494-501.*
Yamamoto et al., “Hierarchical Optical Proximity Correction on Contact Hole Layers,” IEEE, Jul. 13, 2000, pp. 40-41.
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