Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-05-10
2001-02-27
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S702000
Reexamination Certificate
active
06194318
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to manufacture of semiconductor devices. More particularly, this invention relates to processes of making multiple layered wiring structures for large scale integrated (LSI) semiconductor devices. Specifically, the processes employ fusible links (or fuse links). The use of the fuse links is a known redundancy technique utilized in most LSI semiconductor devices.
2. Description of the Related Art
Referring to
FIG. 7
, a known process is explained. A semiconductor substrate
1
has a plurality of wiring layers, as many as 3 wiring layers in this example, over at least one impurity concentrated region (not shown). The wiring layers include a layer functioning as a gate (not shown) of a transistor and a resistor, and a layer interconnecting the gate, the resistor and an appropriate active region of the semiconductor substrate. Each wiring layer is separated from the adjacent wiring layer by an insulator film. The gate has fuse links embedded in an insulator film
3
. Only one of such fuse links is shown at
2
as embedded in the insulator film
3
. Chemical and mechanical polishing, commonly referred to as “CMP”, has been used to smooth a surface of the insulator film
3
. The surface of the insulator film
3
is parallel to the substrate surface and the film thickness is about 1.0 &mgr;m. The wires are produced by forming a mask or positioning a mask over the surface of the insulator film
3
and depositing a metal such as Aluminum (Al). The metal condenses at openings in the mask to form wires and form conductive vias in holes formed through the insulator film to establish electrical connections with a conductive layer underneath. The mask covers area portions in which the fuse links are provided. The wires form a first wiring layer
34
. The thickness of wires of the first wiring layer
34
is about 1.03 &mgr;m. Dielectric material is deposited on the first wiring layer
34
and the remaining area portion of the surface of the insulator film
3
. CMP is used to polish a surface of the deposited dielectric material until the dielectric material as thick as about 1.0 &mgr;m is left above the first wiring layer
34
, thus providing an insulator film
35
. Holes, only one being shown, are formed through the insulator film
35
above the first wiring layer
34
and plugs, only one being shown at
37
, fill the holes in contact with the wires of the first wiring layer
34
. A second wiring layer
38
is formed by Al deposited on the surface of the insulator film
35
. The thickness of the wires of this wiring layer
38
is about 1.6 &mgr;m. A protective material is deposited by plasma CVD to a thickness of 0.8 &mgr;m to form a protective film
19
over the second wiring layer
38
and the remaining area portion of the surface of the insulator film
35
. A photoresist
20
is used as a mask positioning over the protective film
19
. The photoresist
20
has first openings above pads of the second wiring layer
38
and second openings above the fuse links
2
. Using the photoresist
20
as the mask, dry etching is employed to remove or etch portions of the protective film
19
to expose the pads of the second wiring layer
38
and remove portions of the protective film
19
above the fuse links
2
. During this dry etching, portions of the insulator film
35
above the fuse links
2
are removed and portions of the insulator film
3
above the fuse links
2
are thinned to a thickness of about 0.8 &mgr;m above each fuse link
2
to form fuse blow windows. Electric testing is performed using electrical probes in contact with the pads to measure electrical properties of the pads. In response to result of the testing, an appropriate fuse link may be blown by focusing laser energy on the target fuse. The fuse blow window is opened by thinning dielectric material above each fuse link
2
to enhance the probability of completely opening the fuse link upon a laser strike. In the process discussed above, the photoresist
20
can withstand during etching the dielectric material above the fuse link
2
. However, the photoresist
20
may not withstand if the thickness of dielectric material above each fuse link increases further. LSI semiconductor devices may include more than 2 wiring layers and as many as 4 wiring layers separated by insulator (dielectric) films. The known process is not appropriate to manufacturing such LSI semiconductor devices.
Therefore, a need remains to provide a process of making a multiple layered structure of a LSI semiconductor device to allow the use of a mask for dry etching a protective film in thinning the material above a fuse link to provide an appropriate fuse blow window.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a process of making a multiple layered wiring structure, comprising
providing at least one fuse within an area portion of a film over a substrate;
forming a plurality of wiring layers over the remaining area portion of said film, such that each said wiring layer is separated by an insulator film;
forming, by etching, at least one hole through said insulator film for establishing an electrical interconnection between the adjacent two wiring layers separated by said insulator film;
removing, by etching, at least partially said insulator film at a portion above said fuse upon said forming at least one hole;
forming a protective film over said plurality of wiring layers;
forming, by dry etching using a photoresist as a mask, at least one aperture through said protective film to expose a pad of the adjacent wiring layer beneath said protective film;
removing said protective film at a portion above said fuse upon said forming said at least one aperture through said protective film;
conducting testing by contacting an electrical probe with said pad; and
focusing laser energy to said fuse in response to result from said conducting testing.
REFERENCES:
patent: 5729041 (1998-03-01), Yoo et al.
patent: 5965927 (1999-10-01), Lee et al.
patent: 5989784 (1999-11-01), Lee et al.
patent: 6046488 (2000-04-01), Kawasaki et al.
patent: 6054340 (2000-04-01), Mitchell et al.
Chen Kin-Chan
NEC Corporation
Utech Benjamin L.
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