Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Subsequent separation into plural bodies
Reexamination Certificate
2007-09-18
2007-09-18
Thai, Luan (Department: 2891)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Subsequent separation into plural bodies
C438S459000, C257SE21568, C257SE21569, C257SE21570
Reexamination Certificate
active
11007645
ABSTRACT:
A method of manufacturing a thin film integrated circuit device according to the present invention includes steps of forming a peel-off layer over a thermally oxidized silicon substrate, forming a plurality of thin film integrated circuit devices over the peel-off layer with a base film interposed therebetween, forming a groove between the plurality of thin film integrated circuit devices, and separating the plurality of thin film integrated circuit devices by introducing one of a gas and a liquid including halogen fluoride into the groove to remove the peel-off layer.
REFERENCES:
patent: 5206749 (1993-04-01), Zavracky et al.
patent: 5317236 (1994-05-01), Zavracky et al.
patent: 5376561 (1994-12-01), Vu et al.
patent: 5378536 (1995-01-01), Miller et al.
patent: 5389438 (1995-02-01), Miller et al.
patent: 5757456 (1998-05-01), Yamazaki et al.
patent: 5821138 (1998-10-01), Yamazaki et al.
patent: 5834327 (1998-11-01), Yamazaki et al.
patent: 5888858 (1999-03-01), Yamazaki et al.
patent: 5985740 (1999-11-01), Yamazaki et al.
patent: 6043800 (2000-03-01), Sptizer et al.
patent: 6063654 (2000-05-01), Ohtani
patent: 6100562 (2000-08-01), Yamazaki et al.
patent: 6118502 (2000-09-01), Yamazaki et al.
patent: 6165824 (2000-12-01), Takano et al.
patent: 6168829 (2001-01-01), Russ et al.
patent: 6180439 (2001-01-01), Yamazaki et al.
patent: 6348368 (2002-02-01), Yamazaki et al.
patent: 6376333 (2002-04-01), Yamazaki et al.
patent: 6465287 (2002-10-01), Yamazaki et al.
patent: 6479333 (2002-11-01), Takano et al.
patent: 6781152 (2004-08-01), Yamazaki
patent: 6893503 (2005-05-01), Ohnuma et al.
patent: 7045438 (2006-05-01), Yamazaki et al.
patent: 7056381 (2006-06-01), Yamazaki et al.
patent: 7122445 (2006-10-01), Takayama et al.
patent: 7129145 (2006-10-01), Kawamura et al.
patent: 2001/0015256 (2001-08-01), Yamazaki et al.
patent: 2001/0053559 (2001-12-01), Nagao et al.
patent: 2002/0090765 (2002-07-01), Yamazaki et al.
patent: 2003/0022403 (2003-01-01), Shimoda et al.
patent: 2003/0032210 (2003-02-01), Takayama et al.
patent: 2004/0087110 (2004-05-01), Takayama et al.
patent: 2004/0256618 (2004-12-01), Imai et al.
patent: 2005/0037529 (2005-02-01), Nagao et al.
patent: 2005/0042798 (2005-02-01), Nagao et al.
patent: 2005/0095760 (2005-05-01), Yamazaki et al.
patent: 2005/0148121 (2005-07-01), Yamazaki et al.
patent: 0 443 263 (1991-08-01), None
patent: 0 607 709 (1994-07-01), None
patent: 0 607 709 (1994-07-01), None
patent: 0 607 709 (1998-06-01), None
patent: 1 193 759 (2002-04-01), None
patent: 04-351685 (1992-07-01), None
patent: 04-351685 (1992-12-01), None
patent: 2992092 (1992-12-01), None
patent: 06-299127 (1994-10-01), None
patent: 08-096959 (1996-04-01), None
patent: 09-063770 (1997-03-01), None
patent: 2992092 (1999-12-01), None
patent: 2001-030403 (2001-02-01), None
patent: 2001-260580 (2001-09-01), None
patent: 2001-272923 (2001-10-01), None
patent: 2003-203898 (2003-07-01), None
patent: WO 03/010825 (2003-02-01), None
patent: WO 2005/057658 (2005-06-01), None
Search Report of Mar. 15, 2005, European Patent Office for PCT/JP2004/018978.
Written Opinion of Mar. 15, 2005, European Patent Office for PCT/JP2004/018978.
Search Report of Mar. 22, 2005, European Patent Office for PCT/JP2005/001541.
Written Opinion of Mar. 22, 2005, European Patent Office for PCT/JP2005/001541.
“Sense of Crisis” is a Trigger: Ignited Evolution of a Sesame-Grain Sized Chip, Nikkei Electronics, Nov. 18, 2002, pp. 67-76.
T. Shimoda et al.,Surface Free Technology by Laser Annealing(SUFTLA), IEDM 99: Technical Digest of International Electron Devices Meeting, 1999, pp. 289-292.
Kanno Yohei
Takayama Toru
Yamazaki Shunpei
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
Thai Luan
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