Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2002-03-06
2002-10-29
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S372000, C438S564000
Reexamination Certificate
active
06472287
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a process for manufacturing a bipolar transistor.
2. Description of the Prior Art
The structures of bipolar transistors can be classified into two groups; a conventional type and a SST (Super Self-alignment Technology) type. The structure referred to the conventional type is generally made by forming a collector region and a base region in a substrate by the ion implantation technology or the like, and thereafter forming an emitter electrode above it and diffusing thermally dopants from this emitter electrode to form an emitter region in the base region. Referring to
FIG. 7
, the manufacturing method of a bipolar transistor with a conventional structure is described in detail below.
First, as shown in FIG.
7
(
a
), n-type dopants are ion-implanted into the surface of a p-type silicon substrate
1
to form a collector region
2
, and p-type dopants are then ion-implanted to form a base region
3
on the surface of the collector region
2
. Over these, sequentially, an insulating film
4
and a first polycrystalline silicon film
5
are grown in this order (FIG.
7
(
b
)). On this first polycrystalline silicon film
5
, a resist
6
having an opening is formed (FIG.
7
(
c
)), and using this resist as a mask, a contact hole to reach the base region is formed by means of dry etching. In this state,
7
may attach onto the inside of the contact hole (FIG.
7
(
d
)).
Subsequently, ashing and a treatment with a resist-peeling agent are carried out, and then a cleaning using hydrofluoric acid or its salt is carried out, and followed by a rinsing with pure water. Thereby, the resist and the residues from etching
7
are removed. Hereupon, anomalous bodies
8
derived from the remnant solution of hydrofluoric acid after rinsing may reattach onto the first polycrystalline silicon film
5
and the inside of the contact hole (FIG.
8
(
a
)). Next, after a second polycrystalline silicon film
11
is grown over the entire surface of the substrate so as to fill up the inside of the contact hole, n-type dopants are ion-implanted into the second polycrystalline silicon film
11
and, then, by applying a heat treatment to the whole substrate, the n-type dopants are made to diffuse into the base region
3
to form an emitter region
14
. After that, the first polycrystalline silicon film
5
and the second polycrystalline silicon film
11
are shaped into an emitter electrode
15
by selective dry etching, whereby a bipolar transistor is accomplished (FIG.
8
(
b
)).
This conventional technique has, however, the following problems, because anomalous bodies
8
derived from the remnant solution of hydrofluoric acid after rinsing may reattach onto the first polycrystalline silicon film
5
and the inside of the contact hole, as shown in FIG.
8
(
a
). First, when the emitter opening section is formed by dry etching, anomalous bodies lying on the first polycrystalline silicon film serve as a mask, and cause etching remnants. Secondly, since anomalous bodies
8
happen to remain also on the interface between the emitter electrode
15
and the base region
3
, they lead to incomplete diffusion of emitter dopants, and thus in some cases, the emitter region may fail to be formed as designed or the emitter electrode resistance may become high.
Next, the so-called SST (Super Self-alignment Technology) structure is described below. In the SST structure, an outer base region is formed around an emitter in the manner of self-alignment and connected to a base electrode through a polycrystalline silicon film. It is different from the afore-mentioned conventional structure that a polysilicon film for lead of the base is formed on a substrate and a plurality of heat treatments are required to form a base region by thermal diffusion.
FIG. 5
is a process for manufacturing a bipolar transistor with a SST structure, disclosed in Japanese Patent Application Laid-open No. 6-69225. Firstly, an element isolation oxide film
504
is formed on an epitaxial substrate, wherein an n
+
collector buried layer
502
and n
−
collector epitaxial layer
503
are formed on a p-type silicon substrate
501
. Next, after a boron-doped base polysilicon film
505
is grown and then patterned, a silicon oxide film
506
is grown and, in a region where an emitter is to be formed, an opening is formed through the silicon oxide film
506
and the p
+
-type base polysilicon film
505
to expose the n collector epitaxial layer
503
(FIG.
5
(
a
)). Following that, a silicon oxide film is grown over the entire surface and this oxide film is etched by anisotropic etching such as the RIE (Reactive Ion Etching) to form sidewalls
507
of the silicon oxide film. A heat treatment is then applied thereto in a nitrogen atmosphere to form p
+
-type outer base diffusion region
508
(FIG.
5
(
b
)). Next, a polysilicon film
509
that is to serve as an emitter electrode is grown under such a condition that loading of polysilicon deposition apparatus at low temperature or while making hydrogen substitution may allow only little natural oxide film to grow on the interface with the epitaxial layer
503
, and then boron
510
is ion-implanted into this polysilicon film
509
. Subsequently, by applying a lamp heating thereto, for example, at 1050° C. for 60 seconds in a nitrogen atmosphere, boron is made to make solid phase diffusion from the emitter polysilicon film
509
to the n epitaxial layer
503
to form a boron diffusion region
511
that is to serve as an inner base diffusion region (FIG.
5
(
c
)). After that, arsenic
512
is ion-implanted into the polysilicon film
509
and then, by applying a lamp heating thereto, for example, at 1050° C. for 10 seconds in a nitrogen atmosphere, arsenic is made also to make solid phase diffusion from the emitter polysilicon film
509
to the n epitaxial layer
503
to form an emitter diffusion region
513
as well as a base diffusion region
511
′ in the manner of self-alignment (FIG.
5
(
d
)). The emitter polysilicon film
509
is then shaped into an emitter polysilicon electrode
509
by patterning. Finally, an opening is made for a base contact and a metal electrode
514
is plated over the emitter polysilicon electrode
509
′ and the polysilicon electrode
505
for lead of the base and, then, patterned (FIG.
5
(
e
)). The use of the steps of the double diffusion method as described above allows a bipolar transistor with a shallow base diffusion region to be obtained, which decreases various parasitic resistances and capacitances.
While, in order to reduce the emitter resistance, the above process employing the double diffusion method prevent any oxide film from growing on the epitaxial layer
503
, but repeated lamp annealing results in the enlargement of crystalline grains in the emitter polysilicon film
509
that is the very source of diffusion. This single-crystallizing event makes it hard to control the concentrations of the dopants and the depth in the emitter-base junction section, and thus bringing about deviation in the diffusion profile.
As for a process to overcome such a problem, the publication set forth discloses another process for manufacturing, as shown in FIG.
6
. Firstly, following the same steps as a conventional manufacturing process, the fabrication steps proceeds up to the step of forming a Pa diffusion region
103
. In the preceding steps, conditions of pretreatment, loading into a deposition furnace and the like are to be regulated so that such an oxide film
105
as a natural oxide film of a thickness not less than 5 angstroms but not more than 20 angstroms will be formed on the surface that is to become the interface between an epitaxial layer
101
and an emitter polysilicon layer
104
(FIG.
6
(
a
)). Next, keeping the oxide film
105
, an emitter polysilicon film
104
is grown over the entire surface of the epitaxial layer
101
(FIG.
6
(
b
)). After that, boron
106
is ion-implanted into this emitter polysilicon film
104
(FIG.
6
(
c
)). By a
NEC Corporation
Young & Thompson
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