Manufacturing method of semiconductor integrated circuit device

Details Manufacturing method of semiconductor integrated circuit device Manufacturing method of semiconductor integrated circuit device

2003-08-19

2004-11-02

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S762000

Reexamination Certificate

active

06812165

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a technique for manufacturing a semiconductor integrated circuit, particularly a technique effective when applied to the fabrication of a semiconductor integrated circuit device having a step of depositing a silicon nitride film over a substrate by using thermal CVD (Chemical Vapor Deposition).
In a manufacturing process of a highly miniaturized and highly integrated LSI which has been adopted in recent days, a shallow groove isolation (SGI) is formed in a silicon substrate or a contact hole is formed in self alignment with a gate electrode of MISFET (Metal Insulator Semiconductor Field Effect Transistor) by making use of a difference in an etching rate between a silicon oxide film and a silicon nitride film. A formation process of such a shallow groove isolation (SGI) is described, for example, in Japanese Patent Application Laid-Open No. Hei 11(1999)-16999, while a formation process of such a self align contact (SAC) is described, for example, in Japanese Patent Application Laid-Open No. Hei 11(1999)-17147.
It is the common practice to form a silicon nitride film, which is utilized in the forming step of the above-described shallow groove isolation or self align contact, by thermal CVD using monosilane (SiH
4
) and ammonia (NH
3
) as a source gas. As a CVD reactor, employed is a batch-system hot-wall thermal CVD reactor for heat treating a plurality of semiconductor wafers (ex. 100 wafers or so) simultaneously. This hot-wall thermal CVD reactor adopts an indirect heating system of semiconductor wafers (radiation heating of semiconductor wafers by a heater outside a pipe wall) and it has a structure such that the inside wall of a chamber (reaction chamber) and the whole atmosphere in the chamber are heated to a temperature not less than the decomposition temperature of the source gas. In addition, since the source gas must be diffused in a large-volume chamber of this batch-system thermal CVD reactor, this reactor adopts low pressure CVD wherein a film is usually formed under reduced pressure conditions not greater than 0.13 kPa (1 Torr).
The present inventors have investigated on the film forming technique of a silicon nitride film by thermal CVD. The following is the outline of it.
The batch-system hot-wall thermal CVD reactor widely used for the formation of a silicon nitride film is structured to heat the whole atmosphere in the chamber (reaction chamber) so that a reaction product is deposited even on the inside wall of the chamber and becomes a cause for contamination of a wafer. In addition, cumbersome washing must be conducted frequently for removing this deposit from the inside wall of the chamber.
As described above, in the batch-system thermal CVD reactor, film formation is conducted under reduced pressure conditions not greater than 0.13 kPa (1 Torr), which retards a film forming rate. To make up for this retardation, about 100 wafers are treated simultaneously. With a rise in the volume of the chamber accompanied by an increase in the diameter of a wafer, it takes much time to diffuse a source gas uniformly, leading to a deterioration in the through-put of film formation. In a batch-system reactor for simultaneously treating a larger number of wafers, there also occur problems such as difficulty in maintaining a uniform film thickness within the face of the wafer and dislocation of wafer.
Recently, there is a tendency to adopt, as a countermeasure against a reduction in the threshold voltage of the miniaturized MISFET, a so-called dual gate CMOS structure (or also called CMIS (Complementary Metal Insulator Semiconductor)) wherein the gate electrode of an n channel type MISFET is made of n-type polycrystalline silicon and the gate electrode of a p channel type MISFET is made of p-type polycrystalline silicone and both serve as a surface channel type.
In this case, there is a potential danger that by the high temperature heat treatment after formation of a gate electrode, p-type impurity (boron) in the gate electrode made of p-type polycrystalline silicon may be diffused in a semiconductor substrate (well) through a gate oxide film, thereby causing fluctuations in the threshold voltage of MISFET. Deposition of a silicon nitride film after formation of the gate electrode therefore needs precise control of temperature conditions upon film formation. It is however difficult to set temperature conditions precisely in the above-described batch system thermal CVD reactor.
Plasma CVD is known as a method capable of depositing a silicon nitride film at a relatively low temperature without causing fluctuations of the characteristics of MISFET. It however involves drawbacks such as damage of a gate oxide film by plasma and charging up. It is therefore difficult to apply this method to formation of a silicon nitride film for sidewall spacers or silicon nitride film for self align contact.
In a single-wafer thermal CVD reactor which treats wafers one by one in one chamber, on the other hand, the volume of the chamber can be lowered compared with the above-described batch system thermal CVD reactor, which makes it possible to control temperature conditions precisely and improve the uniformity of the film thickness of a large-diameter wafer within its face. In addition, a source gas can be diffused uniformly and promptly even under sub-atmospheric reduced pressure conditions of 1.3 kPa (10 Torr) to 93 kPa (700 Torr), higher than the pressure conditions of the batch-system thermal CVD reactor, which makes it possible to improve a film forming velocity. In addition, by treating wafers one by one, the flow of wafer treatment is not interrupted so that a cycle time of a wafer process can be shortened and work in process can be reduced.
In order to make up for a reduction in the through-put due to treatment of wafers one by one, this single-wafer thermal CVD reactor adopts a cold wall system of heating only the wafer and its vicinity, so that there is not a potential danger of wafers being contaminated with reaction products deposited on the inside wall of the chamber and washing of the inside wall of the chamber is lightened.
Based on these investigation results, the present inventors reach a conclusion that use of a single-wafer cold-wall thermal CVD reactor is effective for the formation of a silicon nitride film required to have highly uniform thickness, for example, a silicon nitride film for side wall spacers or self align contact on a wafer having a diameter as large as about 20 to 30 cm.
The present inventors however found a new problem while investigating the introduction of a single-wafer cold-wall thermal CVD for the manufacturing process of a memory LSI under development.
In general, a memory LSI includes, in one chip, a memory mat and a peripheral circuit. In the memory mat, MISFETs constituting a memory cell are disposed with a markedly high density in order to realize a large-scale memory capacity, while in the peripheral circuit, MISFETs are disposed not so densely. On each of a plurality of chip regions sectioned on a wafer, there appears a region wherein gate electrode patterns are formed with low density (peripheral circuit) and a region with high density (memory mat).
When a silicon nitride film was deposited over such a wafer by thermal CVD, there appeared a phenomenon that in each of the plurality of chip regions, the silicon nitride film over the memory mat is thinner by about 30% than that over the peripheral circuit. This is presumed to occur because the effective surface area per wafer unit area is larger in the high-density region of gate electrodes (memory mat) than in the low-density region (peripheral circuit), which causes, in the former region, a relative shortage in the feed amount of a source gas and in turn, decreases a film deposition amount.
When such a problem (uneven film thickness) occurs, upon formation of side wall spacers on the side walls of the gate electrode of a memory mat or on the side walls of a peripheral circuit or formation of a contact hole in self alignment with the ga

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