Manufacturing method of semiconductor device having high...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S687000

Reexamination Certificate

active

06171957

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and a semiconductor device manufactured thereby and, more specifically, to improvement of a high-pressure reflow process for formation of interconnections of a semiconductor device.
2. Background Art
A conventional manufacturing method of a semiconductor device and the structure of a resulting semiconductor device will be described with reference to FIGS.
3
(
a
)-
3
(
c
).
FIG.
3
(
a
) illustrates the formation in a semiconductor wafer
10
, of an interlayer insulating film
2
on a semiconductor substrate
1
(silicon substrate) on which a semiconductor element (not shown) is formed. Subsequently, a wiring groove
3
and a connection hole
3
a
are formed capable of electrically connecting the semiconductor element on the semiconductor substrate
1
to an upper-layer interconnection (not shown) formed on the interlayer insulating film
2
.
Then, the semiconductor wafer
10
(under manufacture) is placed in a low-pressure atmosphere to remove water, etc. absorbed on the surface, and the temperature is increased. If necessary, the surface of the wafer
10
is thereafter cleaned by etching it by argon inverse sputtering.
Then, a copper film
5
is formed by sputtering. At this time, as shown in FIG.
3
(
b
), a void
8
is formed at the bottom of the connection hole
3
a
in the wiring groove
3
of the semiconductor wafer
10
.
Subsequently, while the semiconductor wafer
10
is heated to 400° C. or higher, a high pressure of about 40-100 MPa is applied. The copper is caused to flow into the void
8
, and the inside of the wiring groove
3
and the connection hole
3
a
is charged with copper.
As shown in FIG.
3
(
c
), the copper film
5
is oxidized (by oxygen or water included in an argon gas) for the application of a high pressure, forming copper oxide film
7
on the surface of the copper film
5
. The oxidation of the copper film S is not limited to its surface, and oxygen diffuses into the inside of the copper film
5
. Thus, the flowability of copper during the application of a high pressure is lowered. As a result, as shown in FIG.
3
(
c
), the void
8
remains even after the high-pressure treatment. That is, filling failure occurs.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problem in the art. An object of the invention is therefore to provide a manufacturing method of a semiconductor device which can prevent oxidation of copper and resulting deterioration of the filling characteristic in a copper high-pressure reflow process of the kind as described above, which is used in wiring of a semiconductor device such as a DRAM or a logic device or in forming an interconnection with the formation of a contact hole or a through-hole, as well as to provide a semiconductor device manufactured by such a method.
According to one aspect of the present invention, in a manufacturing method of a semiconductor device, a wiring groove and/or a connection hole is formed in an interlayer insulating film of a semiconductor wafer. A copper film is formed on the interlayer insulating film so as to cover the wiring groove and/or the connection hole. Then, copper of the copper film is pressure-introduced into the wiring groove and/or into the connection hole by using a high-pressure and high-temperature inert gas. Further, part of the copper film is removed by chemical mechanical polishing, thereby leaving copper only in the wiring groove and/or in the connection hole.
Other and further objects, features and advantages of the invention will appear more fully from the following description.


REFERENCES:
patent: 5011793 (1991-04-01), Obinata
patent: 5447599 (1995-09-01), Li et al.
patent: 5470789 (1995-11-01), Misawa
patent: 5534463 (1996-07-01), Lee et al.
patent: 5572071 (1996-11-01), Lee
patent: 5602053 (1997-02-01), Zheng, et al.
patent: 5635423 (1997-06-01), Huang, et al.
patent: 5654232 (1997-08-01), Gardener
patent: 5864179 (1999-01-01), Koyama
patent: 5877086 (1999-03-01), Aruga
patent: 5877087 (1999-03-01), Mosely et al.
patent: 5880023 (1999-03-01), Jun
patent: 5891803 (1999-04-01), Gardner
patent: 5891804 (1999-04-01), Havemann et al.
patent: 5897370 (1999-04-01), Joshi et al.
patent: 5913146 (1999-06-01), Merchant et al.
patent: 5915421 (1999-06-01), Borzym et al.
patent: 5932289 (1999-08-01), Dobson et al.
patent: 196 14 331 A1 (1997-04-01), None
patent: 2-205678 (1990-08-01), None
patent: 6-275612 (1994-09-01), None
patent: 7-503106 (1995-03-01), None
patent: 7-94507 (1995-04-01), None
patent: 8-172131 (1996-06-01), None
patent: 408203895A (1996-08-01), None
patent: 408241923A (1996-09-01), None
patent: 408293552A (1996-11-01), None
patent: 409219449 (1997-08-01), None
patent: 410125783A (1998-05-01), None
patent: 410125782A (1998-05-01), None
patent: 410172972A (1998-06-01), None
patent: 410242268A (1998-09-01), None
patent: 410256372A (1998-09-01), None
patent: WO 94/13008 (1994-06-01), None
B. Vollmer, T. Licata, D. Restaino, and J. Ryan; “Recent advances in the application of collimated sputtering.” Thin Solid Films, vol. 247 (1994) p. 105, 1994.
Stanley Wolf and Richard N. Tauber, Silicon Processing for the VLSI Era. Lattice Press. p. 191, 1986.
“A Novel High Pressure Low Temperature Aluminum Plug Technology For Sub-0.5 &mgr;m Contact/Via Geometries” by G.A. Dixit et al. IEEE IEDM Technical Digest, 1994, pp. 105-108.
GUTMANN; R.J. (u.a.) Integration of Copper multilevel interconnects with oxide und polymer interlevel dielectrics -In: Thin Solid Films 270, 1995, 472-479.

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