Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2003-01-24
2004-11-09
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S527000, C438S531000, C438S533000, C438S914000, C438S944000
Reexamination Certificate
active
06815318
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and, more specifically, to a manufacturing method of a semiconductor device including an impurity region used for an interconnection structure.
2. Description of the Background Art
A formation method of an impurity region of an interconnection structure applied to common DRAM (Dynamic Random Access Memory) will now be described referring to
FIGS. 12-14
.
Referring to
FIG. 12
, an element isolation region
12
is provided in a surface of a semiconductor layer (including semiconductor substrate)
10
to define an active region. An n-type impurity region
21
and a p-type impurity region
22
doped with impurities are provided in this active region. On the surface of semiconductor layer
10
, a silicon insulating layer
11
provided with a contact hole
51
a
connecting to n-type impurity region
21
and a contact hole
52
a
connecting to p-type impurity region
22
is provided.
A contact plug
51
electrically connected to n-type impurity region
21
is provided within contact hole
51
a
, and a contact plug
52
electrically connected to p-type impurity region
22
is provided within contact hole
52
a
. An n+ type impurity region
21
a
for decreasing a contact resistance with contact plug
51
is formed within n-type impurity region
21
, and a p+ type impurity region
22
a
for decreasing a contact resistance with contact plug
52
is formed within p-type impurity region
22
.
A manufacturing method of a semiconductor device having the above-described structure will briefly be described. Referring to
FIG. 13
, element isolation region
12
is formed in a prescribed region of the surface of semiconductor layer
10
. Thereafter, n-type impurity region
21
and p-type impurity region
22
are formed in the active region of semiconductor layer
10
by impurity implantation.
Silicon insulating layer
11
is then formed on the surface of semiconductor layer
10
. Contact holes
51
a
,
52
a
respectively connecting to n-type impurity region
21
and p-type impurity region
22
are formed in silicon insulating layer
11
using a dry etching method such as a RIE (Reactive Ion Etching) method using a photoresist film on silicon insulating layer
11
having a prescribed opening pattern as a mask using a photolithography technique.
Contact hole
51
a
is then covered with a resist film
14
, and a p-type impurity such as B or BF
2
is implanted into the surface of semiconductor layer
10
through contact hole
52
a
to form p+ type impurity region
22
a.
Referring to
FIG. 14
, after removing resist film
14
, contact hole
52
a
is covered with a new resist film
14
, and an n-type impurity such as P or As is implanted into the surface of semiconductor layer
10
through contact hole
51
a
to form n+ type impurity region
21
a.
Thereafter, contact plugs
51
,
52
, which are made of polysilicon or the like and are electrically connected to n+ type impurity region
21
a
and p+ type impurity region
22
a
respectively, are formed by filling contact holes
51
a
,
52
a.
The aforementioned element isolation region
12
is an isolation region formed by a method such as an embedding method of a thermal oxide film or an oxide film. In addition, silicon insulating layer
11
is an insulator film such as a TEOS (Tetra Etyle Ortho Silicate) oxide film or a nitride film, or a film formed by superimposing these films, which is deposited using a low-pressure or normal-pressure CVD (Chemical Vapor Deposition) method, and has a thickness of about 50 nm-1000 nm.
In the above-described manufacturing method, the impurity region is formed for decreasing the contact resistance using the contact hole. For forming n+ type impurity region
21
a
and p+ type impurity region
22
a
having different conductivity types, however, covering processing using the photolithography technique to cover the other contact hole with a resist film is necessary in each impurity implantation step to semiconductor layer
10
. This increases manufacturing steps and manufacturing cost of the semiconductor device.
SUMMARY OF THE INVENTION
The present invention was made to solve the above-described problem. An object of the present invention is to provide a manufacturing method of a semiconductor device which does not need covering processing using a photolithography technique when impurity regions of different conductivity types are formed using contact holes.
In a manufacturing method of a semiconductor device according to the present invention, a first conductivity type impurity region and a second conductivity type impurity region are included in a semiconductor layer. The method includes the steps of: forming on the semiconductor layer an insulating layer including a first contact hole having a top-end opening shape exposing a surface of the semiconductor layer for an implantation angle of an impurity to a normal of the semiconductor layer and a second contact hole having a top-end opening shape blocking a surface of the semiconductor layer for the implantation angle; implanting an impurity of a first conductivity type into the semiconductor layer with the implantation angle using the insulating layer as a mask to form the first conductivity type impurity region only in a surface portion of the semiconductor layer exposed by the first contact hole; and forming the second conductivity type impurity region only in a surface portion of the semiconductor layer exposed by the second contact hole using the second contact hole of the insulating layer.
According to the above-described manufacturing method of a semiconductor device, when forming first and second impurity regions of different conductivity types using contact holes having different opening shapes, one impurity can be implanted at the first contact hole because the surface portion of the semiconductor layer is exposed for the implantation angle of the impurity to a normal of the semiconductor layer, while the impurity is not implanted at the other contact hole because the surface portion of the semiconductor layer is blocked.
As a result, it is unnecessary to form a conventionally required photoresist to prevent an impurity from being implanted into other regions when the impurity is implanted into a prescribed region. Therefore, manufacturing steps of the semiconductor device can become more simple, and the manufacturing cost can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5972745 (1999-10-01), Kalter et al.
patent: 6291325 (2001-09-01), Hsu
patent: 6518122 (2003-02-01), Chan et al.
patent: 2004/0002203 (2004-01-01), Deshpande et al.
patent: 08-78637 (1996-03-01), None
Hasunuma Eiji
Matsumura Akira
Estrada Michelle
Fourson George
McDermott Will & Emery LLP
Renesas Technology Corp.
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