Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-11-30
2003-12-16
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06665858
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor integrated circuit which include MOS transistors, and particularly to a method of making a gate electrode pattern accurately in compliance with design data.
BACKGROUND OF THE INVENTION
In gaining trends of the microstructuring process of semiconductor integrated circuits, attempts of forming semiconductor regional patterns narrower than the light wavelength often encounter the fluctuation of resulting pattern width against exposure mask patterns. In the case of the gate electrode of a MOS transistor, a wider gate electrode pattern and a resulting increased gate length cause the transistor to operate slower, whereas a narrower gate electrode pattern and a resulting decreased gate length increase the leakage current. Accordingly, the gate electrode pattern of a MOS transistor affects the transistor characteristics significantly.
On this account, for making an intended gate electrode pattern, it is desirable to have the prior simulation-based assessment of the pattern which will be made on a basis of a mask pattern. A variety of test patterns including isolated lines, line bases and line ends of various dimensions are prepared. Masks of these test patterns are used for transfer, etching, etc. in working a wafer, and the dimensions of resulting patterns such as the width are measured at certain positions. The difference of the measured value from the result of optical simulation which is based on design data of the test pattern is evaluated to be a compensation value for the pattern resulting from the simulation, and it is shaped into a model (model expression). In carrying out the simulation for a layout pattern or mask pattern, the result of correction with the model is released as a result of optical simulation.
However, the test pattern used to make the above-mentioned model deals with the pattern shape and working of only single layer and does not consider the influence of its underlay. Specifically, the test pattern is formed as a single-layer film on a mirror wafer or a uniform multi-layer film, and is different from a multi-layer pattern of a semiconductor integrated circuit in which individual regions have different structures. As mentioned above, models used at present are made on the premise of single-layer films and made on a uniform material such as usual mirror wafers, and therefore actual products are partially different from the result of optical simulation.
On this account, the above-mentioned simulation is deficient in reliability and can be used only as assistant means for creating pattern data of exposure masks of gate electrode patterns or for verifying the proximity effect correction.
It is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit which is capable of making gate electrode patterns of MOS transistors accurately in compliance with design data.
These and other objects and novel features of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.
SUMMARY OF THE INVENTION
Among the affairs of the present invention disclosed in this specification, representatives are briefed as follows.
The inventive method of manufacturing a semiconductor integrated circuit having a MOS transistor includes a step of exposing a semiconductor substrate to a gate electrode pattern of the MOS transistor through an exposure mask which has the prior rendition of pattern shape assessment based on optical simulation. The pattern shape assessment is carried out by optical simulation of a gate electrode pattern based on pattern data of layout design of the semiconductor integrated circuit. The model-based correction is applied to the optical simulation for the pattern shape assessment. The model for the pattern shape assessment is formed by comparing test patterns with light intensity patterns and defines compensation values correlative to dimensional differences of the light intensity patterns from the test patterns. The test patterns are formed on a basis of test pattern data above different underlays on a test wafer and the light intensity patterns are formed by optical simulation based on test pattern data.
The assessment is based on the use of test patterns depending on different vertical structures of individual underlying layers, in contrast to the conventional case where a same test pattern is used for different underlays of idea semiconductor integrated circuit. For example, for a gate layer, different etching rates are used above an n-type semiconductor region (n+) and above a p-type semiconductor region (p+), and therefore test patterns are made separately for the n+ and p+ regions even if their pattern dimensions are equal. Optical simulation is carried out by selecting a model in consideration of the layout structure below the gate electrode pattern which is the subject of simulation.
The foregoing verification scheme takes account of the influence of underlay of pattern on the etching rate or the like, which has not been considered in the conventional optical simulation, in optical simulation by use of models based on multi-layer test patterns, whereby the simulation accuracy of gate electrode patterns can be improved. Accordingly, by using exposure masks of gate electrode patterns made under the foregoing verification for the manufacturing of a semiconductor integrated circuit, it becomes possible to form gate electrode patterns of MOS transistors accurately in compliance with design data.
By separating the effects of different underlays, such as the reflection (shift of exposure strength) and steps (defocus) which can be corrected directly in optical manner, from other effects such as etching rate, and making models based on the calculation by optical simulation from the reflectivity and step value, instead of being based on test patterns, for the affairs which can be corrected directly in terms of optical effect, or based on the calculation by optical simulation for individual affairs, it is possible to eliminate the need of models.
At a border section between different underlays, the model is not switched in discontinuous manner. Instead, a model of the worst value (a model of a large dimensional correction value), a model of the best value (a model of a small dimensional correction value), a model of a mean value of the best and worst values, a model of a continuous linear function of the best and worst values, etc. are prepared so as to be selected depending on the purpose of simulation. For example, in the case of automatic correction by proximity effect correction based on the optical simulation result, the use of worst value is not desirable due to the possibility of over-correction attributable to other error factors such as mask misalignment. In another case where optical simulation is used for pattern verification, the use of worst value is necessary. Based on this treatment of border section, the accuracy of simulation of layout pattern is further improved.
For a border section, in case an accurate model cannot be made due to the variation of thickness at a step or the presence of halation, it is alternatively possible to apply additionally a geometrical operation such as dimensional shift by a constant value.
REFERENCES:
patent: 5525534 (1996-06-01), Ikemasu et al.
patent: 6038020 (2000-03-01), Tsukuda
patent: 6334209 (2001-12-01), Hashimoto et al.
patent: 6391501 (2002-05-01), Ohnuma
Hitachi , Ltd.
Lin Sun James
Mattingly Stanger & Malur, P.C.
Smith Matthew
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