Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2006-12-27
2009-11-24
Garber, Charles D. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S116000, C438S597000, C438S637000, C438S671000, C438S761000, C257SE21038, C257SE21039, C257SE21314
Reexamination Certificate
active
07622336
ABSTRACT:
To provide a manufacturing method of a semiconductor device with a reduced chip area by reducing the size of a pattern for forming an integrated circuit. For example, the size of an IC chip that is provided as an application of IC cards or IC tags can be reduced. The manufacturing method includes the steps of forming a gate electrode; forming an insulating layer over the gate electrode; and forming an opening in the insulating layer. One or both of the step of forming the gate electrode and the step of forming the opening in the insulating layer is/are conducted by a lithography process using a phase-shift mask or a hologram mask. Accordingly, micropatterns can be formed even over a substrate with low planarity such as a glass substrate.
REFERENCES:
patent: 5573890 (1996-11-01), Spence
patent: 5702848 (1997-12-01), Spence
patent: 5766804 (1998-06-01), Spence
patent: 5766806 (1998-06-01), Spence
patent: 5945237 (1999-08-01), Tanabe
patent: 6645856 (2003-11-01), Tanaka et al.
patent: 6875689 (2005-04-01), Wu
patent: 2002/0006555 (2002-01-01), Hasegawa et al.
patent: 2002/0025591 (2002-02-01), Ohnuma et al.
patent: 2003/0039896 (2003-02-01), Iriguchi
patent: 2004/0151993 (2004-08-01), Hasegawa et al.
patent: 2005/0001253 (2005-01-01), Sugimura
patent: 2005/0040531 (2005-02-01), Kurokawa
patent: 2005/0134463 (2005-06-01), Yamazaki
patent: 2006/0014335 (2006-01-01), Ohnuma et al.
patent: 2006/0186409 (2006-08-01), Horino et al.
patent: 2006/0240334 (2006-10-01), Huh et al.
patent: 1115876 (1996-01-01), None
patent: 0698916 (1996-02-01), None
patent: 05-005978 (1993-01-01), None
patent: 05-090130 (1993-04-01), None
patent: 2005-202947 (2005-07-01), None
Suganuma et al., “A 200 nm X2 mm array of organic light-emitting diodes and their anisotropic electroluminescence”, Applied Physics Letters, 1999 American Institute of Physics, Mar. 1, 1999, vol. 74, No. 9, pp. 1206-1208.
Chinese Office Action (Application No. 200610172809.8; CN9313) Dated May 22, 2009.
Ahmadi Mohsen
Costellia Jeffrey L.
Garber Charles D.
Nixon & Peabody LLP
Semiconductor Energy Laboratory Co,. Ltd.
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