Manufacturing method of CMOS thin film transistor

Details Manufacturing method of CMOS thin film transistor Manufacturing method of CMOS thin film transistor

2003-09-26

2004-09-14

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S154000, C438S164000

Reexamination Certificate

active

06790715

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin filmtransistor (TFT) process, and more particularly, to a method of forming a complementary metal oxide semiconductor thin film transistor (CMOS TFT).
2. Description of the Related Art
In TFT-LCDs, a polycrystalline silicon (poly-Si) TFT formed on a quartz substrate or an amorphous silicon (a-Si) TFT formed on a large size glass substrate is mostly used. The TFTs in TFT-LCDs are used in one instance for a TFT matrix in a display portion and in another instance for formation of an outer circumferential circuit (also referred to as a driver circuit) on a common substrate for driving such a TFT matrix. In the former instance, an n channel TFT is used, and in the latter instance, a CMOS TFT is used for achieving high speed operation.
The CMOS TFT includes an n-type TFT (NMOS TFT) and a p-type TFT (PMOS TFT). In order to decrease the “OFF current” of the NMOS TFT, an LDD (lightly doped drain) structure is usually designed therein. Hereinafter, a conventional CMOS TFT process will be described, with reference to FIGS.
1
A~
1
F.
In
FIG. 1A
, a glass substrate
100
having a predetermined NMOS area
110
and a predetermined PMOS area
120
is provided. By performing a first patterning procedure with a first photomask (or reticle), a first polysilicon layer
130
and a second polysilicon layer
135
are formed on part of the substrate
100
.
The first polysilicon layer
130
is located in the NMOS area
110
and the second polysilicon layer
135
is located in the PMOS area
120
.
In
FIG. 1B
, by performing a second patterning procedure with a second photomask, a photoresist layer
140
is formed on the first polysilicon layer
130
or the second polysilicon layer
135
. As an example, the second polysilicon layer
135
is herein covered with the photoresist layer
140
. Then, an ion implantation procedure
150
, such as a p
−
-ion doping procedure, is performed to adjust threshold voltage. That is, this step functions as a threshold voltage adjustment (V
t
adjustment). Symbol
131
indicates an adjusted first polysilicon layer.
In
FIG. 1C
, the photoresist layer
140
is removed. By performing a third patterning procedure with a third photomask, a photoresist layer
155
is formed on part of the first polysilicon layer
131
and over the second polysilicon layer
135
. Then, an n
+
-ion doping procedure
160
is performed to form an n
+
-polysilicon film
170
in part of the first polysilicon layer
131
. The n
+
-polysilicon film
170
serves as the source/drain region of the NMOS area.
In
FIG. 1D
, the photoresist layer
155
is removed. A gate insulating layer
180
is formed on the first polysilicon layer
131
, the second polysilicon layer
135
and the substrate
100
. Then, a metal layer (not shown) is formed on the gate insulating layer
180
. By performing a fourth patterning procedure with a fourth photomask, the metal layer (not shown) is patterned to form a first gate
190
and a second gate
195
. The first gate
190
is located in the NMOS area
110
and the second gate
195
is located in the PMOS area
120
.
In
FIG. 1D
, using the first gate
190
and second gate
195
as a mask, an n
−
-ion doping procedure
200
is performed to form n
−
-polysilicon film
210
in part of the first polysilicon layer
131
and part of the second polysilicon layer
135
. The n
−
-polysilicon film
210
, located in the NMOS area
110
, serves as the lightly doped drain (LDD) region of the NMOS TFT.
In
FIG. 1E
, by performing a fifth patterning procedure with a fifth photomask, a photoresist layer
220
is formed to cover the NMOS area
110
. Using the photoresist layer
220
as a mask, a p
+
-ion doping procedure
230
is then performed to form a p
+
-polysilicon film
240
in part of the second polysilicon layer
135
. The p
+
-polysilicon film
240
serves as the source/drain region of PMOS.
Next, the photoresist layer
220
is removed. Thus, an NMOS device
250
is formed in the NMOS area
110
and a PMOS device
255
is formed in the PMOS area
120
.
In
FIG. 1F
, a passivation layer
260
is thoroughly formed to cover the NMOS device
250
and the PMOS device
255
. By performing a sixth patterning procedure with a sixth photomask, a plurality of contact holes
270
penetrating the passivation layer
260
and the gate insulating layer
180
are formed. The contact holes
270
expose the source/drain region
170
of the NMOS device
250
and the source/drain region
240
of the PMOS device
255
. Finally, a conductive material is filled in the contact holes
270
to form a plurality of plugs
280
.
The method for fabricating the above comprises six patterning (or photolithography and etching) steps. That is, the conventional method requires six photomasks or photomasks, which increases costs. In order to decrease manufacturing costs, a method which consumes fewer photomasks than the conventional method is called for.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method of forming a CMOS TFT, which requires fewer photomasks than the prior art.
Another object of the present invention is to provide a method of forming a CMOS TFT with five photomasks (or five photolithography steps).
In order to achieve these objects, the present invention provides a method of forming a CMOS TFT device. A substrate having a predetermined NMOS area and a predetermined PMOS area is provided, wherein the NMOS area includes a first doped area, a lightly doped area and a first gate area, and the PMOS area includes a second doped area and a second gate area. By performing a first patterning procedure with a first photomask, a first semiconductor island and a second semiconductor island are formed on part of the substrate, wherein the first semiconductor island is located in the NMOS area and the second semiconductor island is located in the PMOS area. By performing a second patterning procedure with a second photomask, the first semiconductor island and/or the second semiconductor island is exposed. Impurities are doped into the exposed first semiconductor island and/or the exposed second semiconductor island to adjust threshold voltage. An insulating layer is formed on the first semiconductor island, the second semiconductor island and the substrate. A conductive layer is formed on the insulating layer. By performing a third patterning procedure with a third photomask, part of the conductive layer is removed to define a first gate and a second gate, wherein the first gate is located in the first gate area and the second gate is located in the second gate area. Using the first gate and the second gate as a mask, an n
−
-ion doping procedure is performed to form an LDD region in the first semiconductor island and in the lightly doped area. The PMOS area is exposed by performing a fourth patterning procedure with a fourth photomask. Using the second gate as a mask, a p
+
-ion doping procedure is performed to form a second source/drain region in the second semiconductor island and in the second doped area. A passivation layer is formed on the insulating layer, the first gate and the second gate. By performing a fifth patterning procedure with a fifth photomask, and a first contact hole, a second contact hole, a third contact hole and a fourth contact hole penetrating the passivation layer and the insulating layer are formed, wherein the first and second contact holes correspond to the first doped area, and the third and fourth contact holes are located on the second source/drain region. By means of the first, second, third and the fourth contact holes, an n
+
-ion doping procedure is performed to form a first source/drain region in the first semiconductor island and in the first doped area, wherein an ion dosage of the p
+
ions doping procedure is greater than an ion dosage of the n
+
ions doping procedure.
The present invention improves on the prior art in that the present method uses only five photo

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