Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-09-07
2001-09-04
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S257000, C438S586000
Reexamination Certificate
active
06284638
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, particularly to a semiconductor device comprising an insulated-gate field effect transistor having a contact hole formed in an inter-layer insulating film on a source/drain region (hereinafter refered to as S/D region) adjacent to a gate electrode.
2. Description of the Prior Art
A higher integration level has been requested for a semiconductor memory in recent years, therefore, it is necessary to further fine a pattern. As one of the means for realizing a higher integration level, an insulated-gate field effect transistor is further fined which serves as a component of the semiconductor memory.
FIG. 1A
to
FIG. 1F
are sectional views for explaining a method for manufacturing an insulated-gate field effect transistor having a contact hole formed in an inter-layer insulating film on an S/D region of both sides of a gate electrode. The insulated-gate field effect transistor uses an insulated-gate field effect transistor having a floating gate in an EPROM cell.
FIG. 1A
shows a state after a floating gate and a control gate are formed and moreover a S/D region is formed in a surface layer of a semiconductor substrate of both sides of the control gate.
In
FIG. 1A
, symbol
1
is a semiconductor substrate,
2
is a gate insulating film on the semiconductor substrate
1
,
3
a
is a floating gate on the gate insulating film
2
,
3
c
is a control gate formed above the floating gate
3
a
through an insulating film
3
b
,
4
is an insulating film on the control gate
3
c
, and
5
a
and
5
b
are S/D regions formed in the surface layer of the semiconductor substrate
1
of both sides of the control gate
3
c.
Under the above state, as shown in
FIG. 1B
, an insulating film
6
is formed by covering the gate insulating film
2
, floating gate
3
a
, insulating film
3
b
, and control gate
3
c
in order to form a side wall.
Then, as shown in
FIG. 1C
, an insulating side wall
6
a
is formed on the side surface of the gate electrode
3
by anisotropically etching the insulating film
6
.
Then, as shown in
FIG. 1D
, an inter-layer insulating film
7
is formed on the entire surface.
Then, as shown in
FIG. 1E
, the inter-layer insulating film
7
on the S/D region
5
a
is selectively etched and removed to form a contact hole
7
a
in the inter-layer insulating film
7
on the S/D region
5
a.
Then, as shown in
FIG. 1F
, a conducting film is formed and thereafter patterned to form a source/drain electrode (hereinafter refered to as S/D electrode) or interconnection layer
8
which connects with the S/D region
5
a
through the contact hole
7
a.
For the above existing method for fabricating a semiconductor device, however, it is necessary to decrease the size of the S/D regions
5
a
and
5
b
and bring the contact hole
7
a
as closely to the gate electrode
3
as possible in order to integrate elements at a high density. For this reason, in the case that a deviation of an alignment occurs when patterning a contact hole, the contact hole
7
a
may be formed by etching the side wall
6
a
as shown in FIG.
2
.
Therefore, when an S/D electrode or interconnection layer is formed in the contact hole
7
a,
the thickness of an insulating film between the gate electrode
3
and the S/D electrode or interconnection layer fluctuates. For this reason, a problem occurs that parasitic capacitance fluctuates or accumulated electric charges fluctuate due to leakage of them.
Besides, an existing example is shown in a patent document of the Japanese unexamined publication (KOKAI) 3-96271. In this case, the same problem as described above might occur, too.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an insulated-gate field effect transistor for securing the uniformity of the thickness of an insulating film put between the side surface of a gate electrode and an S/D electrode or interconnection layer while integrating elements at a high density and its manufacturing method.
The insulated-gate field effect transistor according to the present invention has a conducting side wall covering an insulating side wall of a gate electrode of the side where a contact hole is formed and contacting an S/D region.
Therefore, even if a deviation of an alignment occurs and the contact hole to the S/D region approaches the gate electrode, it is brought onto the conducting side wall. Thus, when an S/D electrode is formed in the contact hole, only the insulating side wall remains as an insulating film actually put between the S/D electrode and gate electrode because the S/D electrode contacts the conducting side wall. Therefore, its thickness becomes constant independently of the position of the contact hole.
Moreover, in case that the contact hole goes away from the gate electrode, the conducting side wall is covered with a covering insulating film and the S/D electrode formed in the contact hole does not contact the conducting side wall. Even in this case, as both the conducting side wall and S/D electrode contact the S/D region, the conducting side wall and the S/D electrode have the same potential, so that only the insulating side wall remains as an insulating film actually present between the S/D electrode and gate electrode. Thereby, its thickness becomes constant independently of the position of the contact hole.
Furthermore, when forming by introducing impurities a bulk interconnection layer in the semiconductor layer of a side where no contact hole is formed, the second conducting side wall is left at the side where no contact hole is formed and serves as a mask for etching a natural oxide film and introducing impurities while the semiconductor layer is masked at the side where a contact hole is formed.
Thus, the allowance for mask alignment increases and the mask is easily formed. Moreover, a sufficient distance between a channel region under the gate electrode and a bulk interconnection layer is secured so that preventing a channel length from becoming short and a gate control voltage from fluctuating.
REFERENCES:
patent: 5132758 (1992-07-01), Minami et al.
patent: 5146291 (1992-09-01), Watabe et al.
patent: 5194929 (1993-03-01), Ohshima et al.
patent: 5429969 (1995-07-01), Chang
patent: 5679590 (1997-10-01), Mori et al.
patent: 5804838 (1998-09-01), Manning
patent: 5821143 (1998-10-01), Kim et al.
patent: 5649570 A (1981-05-01), None
patent: 56135971 A (1981-10-01), None
patent: 6153775 (1986-03-01), None
patent: 3-96271 (1991-04-01), None
Armstrong Westerman Hattori McLeland & Naughton LLP
Fourson George
Fujitsu Limited
Garcia Joannie Adelle
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