Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2005-07-19
2009-02-10
Zarneke, David A (Department: 2891)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S014000, C257S620000, C257SE21599, C257SE23179
Reexamination Certificate
active
07488668
ABSTRACT:
With use of a length-dimension of a second-line-segment of a unit-device-formation-region as an arrangement interval, a plurality of parallel lines are disposed in a device-formation-effective-region on a wafer so as to form a plurality of parallel-line-partition-regions, the unit-device-formation-regions are arranged in each of the parallel-line-partition-regions independently of and separately from other parallel-line-partition-regions so that the acquisition number of the unit-device-formation-regions is maximized, and an arrangement of the respective unit-device-formation-regions in the respective parallel-line-partition-regions is determined as an arrangement of the entire device-formation-effective-region.
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Chien C-F, et al., entitled “A Cutting Algorithm for Optimizing the Wafer Exposure Pattern”, IEEE Transactions on Semiconductor Manufacturing, IEEE Inc., New York, US, vol. 14, No. 2, May 2001, pp. 157-162, XP001081178.
Arita Kiyoshi
Haji Hiroshi
Nakagawa Akira
Nishinaka Teruaki
Noda Kazuhiro
Panasonic Corporation
Wenderoth , Lind & Ponack, L.L.P.
Zarneke David A
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