Manufacturing method for semiconductor device

Details Manufacturing method for semiconductor device Manufacturing method for semiconductor device

2011-08-23

2011-08-23

Duda, Kathleen (Department: 1722)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S005000, C430S394000

Reexamination Certificate

active

08003301

ABSTRACT:
A manufacturing method for a semiconductor device having patterns including two adjacent sides forming a corner portion with an external angle and a periodic pattern with a high density arrangement in the same layer is provided with (a) the step of exposing the first divided pattern including a first side which is obtained by dividing the pattern including two sides and the region which corresponds to a first thinned out pattern from which the periodic pattern is thinned out to light through a first mask having a first mask pattern, and (b) the step of exposing the second divided pattern including a second side which is obtained by dividing the pattern including two sides and the region which corresponds to a second thinned out pattern which is obtained by thinning out the periodic pattern to light through a first mask having a second mask pattern.

REFERENCES:
patent: 6998201 (2006-02-01), Koike
patent: 2007/0018286 (2007-01-01), Chen
patent: 11-135417 (1999-05-01), None
Colburn, M. et al., “Process Challenges for Extension of H2O Immersion Lithography to Hyper-NA.” Sematech Litho Forum, May 22, 2006. IBM Corporation 2004.
Arnold, Bill. “ASML ArF Immersion Tool Development and Status.” Sematech Litho Forum, Vancouver, May 23, 2006.
Kameyama, M. “ArF Immersion and Extension.” Nikon Corporation. The 2006 Litho Forum, May 23, 2006.
Schellenberg, Franklin M. “Managing RET Complexity Under Immersion.” Mentor Graphics. Sematech Litho Forum, May 23, 2006.
Hendrickx, Eric, et al. “Complementary dipole exposure solutions at 0.29 k1.” Proceedings of SPIE 2005, vol. 5754-32.
Maenhoudt, M. et al. “Double Patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75.” Proceeding of SPIE 2006, vol. 5754-203.
Lim, Chang-Moon et al. “Positive and Negative Tone Double Patterning Lithography for 50nm Flash Memory.” Proceedings of SPIE 2006, vol. 6154-37.

Affiliated with

Also associated with

Rating

Manufacturing method for semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Manufacturing method for semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacturing method for semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2706578