Manufacturing method for semiconductor chips and...

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

Reexamination Certificate

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C438S011000, C438S018000, C257SE21524

Reexamination Certificate

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07989803

ABSTRACT:
In a semiconductor wafer that has semiconductor devices arranged in a plurality of device-formation-regions and a TEG placed in dividing regions that define the device-formation-regions, a TEG-placement portion is arranged in the dividing regions partially expanded in width, and the TEG is placed in the TEG-placement portion. Additionally, a protective sheet is stuck to the semiconductor wafer, then plasma etching is performed, and the TEG is removed in a state where it remains in the dividing region and stuck to the protective sheet together with the protective sheet by peeling off the protective sheet, thereby the device-formation-regions are divided into individual pieces, and the semiconductor chips are manufactured.

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Patent Cooperation Treaty (PCT) International Preliminary Report on Patentability, issued Jul. 17, 2007 in International Application No. PCT/JP2006/300409.

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