Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-06-21
2001-05-22
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S587000, C438S592000, C438S624000, C438S627000, C438S629000
Reexamination Certificate
active
06235619
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, and more particularly to a semiconductor device manufacturing method that includes a contact hole forming process.
2. Description of Related Art
In a semiconductor device that is manufactured by forming multiple films on a substrate, contact holes are usually formed to connect a wire in an upper layer with a wire or an electrode in a lower layer. These contact holes are usually constructed by forming a resist pattern on the upper layer using a lithography process and then performing an etching process until the lower layer is exposed.
However, the conventional semiconductor device manufacturing method has problems. For example, the resist pattern is occasionally displaced when it is formed, and a portion of the silicon oxide film of the device separation unit is occasionally removed when a silicon nitride film that is used as an etching stopper is over-etched. Given these problems, in order to prevent the device characteristics and the manufacturing yield from deteriorating, the structure of the semiconductor device is determined taking the margin of alignment into consideration.
As the semiconductor device is scaled down, the dimensions of the structure of the semiconductor device such as the width of the activation region between device separation regions, the width of the transfer gate, the size of the contact hole, and the like are being scaled down also. However, the margin of alignment is not being scaled down accordingly. Therefore, the margin of alignment is one of the major factors preventing a further scale reduction of the semiconductor device.
SUMMARY OF THE INVENTION
Given these problems, it is an object of the present invention to provide a semiconductor device manufacturing method capable of solving these problems.
To solve the above-stated problems, a semiconductor device manufacturing method according to the present invention has the following steps. First, in the depositing process, at least a first layer, a second layer, and a third layer are formed in sequence. The second layer and the third layer are laminated in sequence over the first layer so as to cover plural gate electrodes formed on the first layer. Second, in the first etching process, an opening unit is formed between the gate electrodes, and the third layer is etched using the second layer as an etching stopper. Third, in the depositing process, an insulating material film is deposited on the side wall of the opening unit and the bottom portion of the opening unit to a thickness with which the insulating material film functions as a spacer for the insulation. Fourth, in the second etching process, a contact hole is formed by anisotropically etching the insulating material film deposited at the bottom portion of the opening unit and the second layer beneath the insulating material film to expose the first layer.
REFERENCES:
patent: 5175120 (1992-12-01), Lee
patent: 5668052 (1997-09-01), Matsumoto et al.
patent: 5792705 (1998-08-01), Wang et al.
Chaudhuri Olik
Jones Volentine, LLC
OKI Electric Industry Co., Ltd.
Rao Shrinivas H.
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