Manufacturing method for planar independent-gate or...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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Details

C438S176000, C438S195000, C438S283000, C438S588000, C257SE21179

Reexamination Certificate

active

07923315

ABSTRACT:
The present invention relates to a method for fabricating a planar independent-double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction.

REFERENCES:
patent: 5583362 (1996-12-01), Maegawa
patent: 5965914 (1999-10-01), Miyamoto
patent: 7002207 (2006-02-01), Kim et al.
patent: 7800172 (2010-09-01), Lee et al.
patent: 2004/0124468 (2004-07-01), Coronel et al.
patent: 2004/0262690 (2004-12-01), Coronel et al.
patent: 2009/0212330 (2009-08-01), Bernard et al.

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