Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-10-09
2003-06-17
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S163000, C438S164000, C438S174000, C438S217000, C438S301000, C438S305000
Reexamination Certificate
active
06579750
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to silicon-on-insulator (SOI) semiconductor devices and more particularly to fully depleted SOI transistors.
BACKGROUND ART
In silicon semiconductor technology, the only way to achieve insulating substrates is by resorting either to silicon on insulator (SOI), silicon on sapphire (SOS), or etch and bond back to achieve SOI. The advantages of using an insulating substrate in CMOS and high speed field effect transistors (FETs) include latchup immunity, radiation hardness, reduced parasitic junction capacitance, reduced junction leakage currents and reduced short channel effects. Many of these advantages translate to increased speed performance of the FETs.
The SOI FETs are manufactured with an insulator, such as silicon dioxide, on a semiconductor substrate, such as silicon. The entire FETs, including their source, channel, drain, gate, ohmic contacts and channels, are formed on silicon islands in the insulator, and are insulated from any fixed potential. This results in what is called the “floating body” problem because the potential of the body or channel regions float or acquire a potential which can interfere with the proper functioning of the FETs. The floating body problem causes high leakage current and parasitic bipolar action since the semiconductor substrate is floating with respect to the channel. This problem has adverse affects on threshold voltage control and circuit operation.
In order to eliminate the floating body problem, it is necessary to fully deplete the silicon island. This means that the silicon island is sufficiently thin that the entire thickness of the body region is depleted of majority carriers when the FET is in the off state and both junctions are at ground. To be able to fully deplete the silicon island, it has been found that the silicon island must be extremely thin and in the order of 200 Å for a 50 nm SOI FET.
Unfortunately, silicon islands of 200 Å thickness are extremely difficult and costly to make. Further, at this thickness, the formation of the silicide necessary for the source/drain contacts to connect to the transistor may totally convert the silicon into silicide which would result in high resistance source/drain junctions.
Numerous attempts have been made to for fully depleted SOI FETs which avoid the thin silicon islands. Some designs provide body-substrate contacts to tie the body to a fixed potential. For example, some designs provide the body-substrate contact in the channel region, however, the since the gate remains capacitively coupled to both bulk charge and SOI charge, the advantages of an SOI are lost.
A solution to the above problems has long been sought, but only partially depleted SOI FETs have been introduced into production. A truly fully depleted SOI has long eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides a silicon on insulator (SOI) semiconductor device having a semiconductor substrate with an inverted region, an insulator, and a silicon island. The device combines the inverted region with channel doping to fully deplete the silicon island of majority carriers when the device is in the off state and both of its junctions are at ground.
The present invention provides method of manufacturing a silicon on insulator (SOI) semiconductor device having a semiconductor substrate with an inverted region, an insulator, and a silicon island. The method provides the inverted region and channel doping to fully deplete the silicon island of majority carriers when the device is in the off state and both of its junctions are at ground.
REFERENCES:
patent: 5208168 (1993-05-01), Parrillo et al.
patent: 5359219 (1994-10-01), Hwang
patent: 6190982 (2001-02-01), Tseng et al.
patent: 6342423 (2002-01-01), Ishida et al.
Cao Phat X.
Doan Theresa T.
Ishimaru Mikio
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