Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2006-07-25
2006-07-25
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S692000, C438S756000, C430S313000, C216S080000, C216S089000, C216S097000
Reexamination Certificate
active
07081417
ABSTRACT:
To provide a planarization method which does not depend upon the size and the density of a wiring pattern and in which a reliable wiring system and a Josephson device can be formed and wiring structure, an insulation layer is planarized by forming a reversal pattern mask of wiring and selectively removing the insulation layer on the wiring.
REFERENCES:
patent: 4075756 (1978-02-01), Kircher et al.
patent: 7-147278 (1993-11-01), None
patent: 2003-324221 (2002-05-01), None
S. Nagasawa et al., “Planarization Technology for Josephson Integrated Circuits”, IEEE Electron Device Letters, vol. 9, No. 8 (Aug. 1988), pp. 414-416.
M. B. Ketchen et al., “Sub-μm, Planarized, Nb-AlOx-Nb Josephson Process for 125 mm Wafers Developed in Partnership with Si Technology”, Appl. Phys. Lett., vol. 59, No. 20 (Nov. 11, 1991), pp. 2609-2611.
K. Kikuchi et al., “New Fabrication Process of Josephson Tunnel Junctions Using Photosensitive Polyimide Insulation Layer for Superconducting Integrated Circuits”, ASC (2002), pp. 1-4.
Hidaka Mutsuo
Hinode Kenji
Kitagawa Yoshihiro
Nagasawa Shuichi
Tanabe Keiichi
A. Marquez, Esq. Juan Carlos
Angadi Maki
Fisher Esq. Stanley P.
Hitachi , Ltd.
International Superconductivity Technology Center, the Judicial
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