Manufacturing method for a self-aligned through hole and semicon

Details Manufacturing method for a self-aligned through hole and semicon Manufacturing method for a self-aligned through hole and semicon

1995-01-17

1995-10-24

Powell, William

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

H01L 21306, B44C 122, C03C 1500

Patent

active

054606900

ABSTRACT:
A self-aligned through hole (5), particularly a bit line through hole to a source/drain region (2) that is self-aligned relative to the word line, is produced in neighboring word lines (3a) having a greater spacing from one another in the proximity of the source/drain region than at other locations. Narrow spacings are completely filled by surface-wide deposition of an insulating intermediate layer and subsequent, anisotropic etching, whereas insulating spacers (4") are formed in enlarged interspaces at side walls of the encapsulated word lines (3) and thereby form a self-aligned through hole.

REFERENCES:
patent: 5043781 (1990-08-01), Nishiura et al.
patent: 5094900 (1992-03-01), Langley
patent: 5275972 (1994-01-01), Ogawa et al.
Research Disclosure 32246 disclosed anonymously Feb. 1991.
IBM Technical Disclosure Bulletin, vol. 31, No. 2, Jul. 1988, "Process for Making Conductice Lines of Two Different Materials Within a Level of Wiring", (1988) pp. 34-35.
IEEE Journal of Solid-State Circuits, vol. SC018, No. 3, Jun. 1983, "A 256 kbit ROM with Serial ROM Cell Structure", Roger Cuppens et al, pp. 340-344.
Symposion in VLSI Technology 1987, Japan, "A High Density 4Mbit dRAM Process Using a Fully Overlapping Bitline Contact (FoBIC) Trench Cell", by Kuesters et al, pp. 93-94.

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