Manufacturing method for a DRAM cell

Details Manufacturing method for a DRAM cell Manufacturing method for a DRAM cell

1992-01-22

1993-02-02

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437228, 437233, 437235, 437919, H01L 2170

Patent

active

051837722

ABSTRACT:
A manufacturing method for a DRAM cell provided with a stacked capacitor is disclosed. The method including: (1) defining a switching transistor region by forming a field oxide layer upon a first conduction type semiconductor substrate; (2) forming source and drain regions of a second conduction type; (3) forming respective first conductive layers on a part of said field oxide layer and on a gate oxide layer over a channel region within the switching transistor region; and forming a first insulating layer; (4) forming a second conductive layer and removing parts of the second conductive layer which are over the channel region and the drain region; (5) forming an opening for exposing a part of the source region; (6) forming a third conductive layer on the substrate and overlapping the remaining portions of the second conductive layer, to provide a portion thereof having a saddle structure providing a gentle slope; (7) etching to remove portions of the second and third conductive layers; (8) forming a dielectric layer; and (9) forming a fourth conductive layer.

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Koyamagi et al. A 5-V only 16 k-bit stacked-capacitor MOS RAM.
Watanabe, "Stacked capacitor cells for high-density dynamic RAMS", IEDM 1988 pp.-600-603.
Ghate, "Interconnections in VLSI" Physics Today Oct. 1986 pp. 58-66.

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