Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-12-08
2001-02-13
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S301000, C438S303000, C438S595000
Reexamination Certificate
active
06187674
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a manufacturing method capable of preventing the corrosion and contamination of a MOS gate. More particularly, the present invention relates to a manufacturing method that uses a rapid thermal process to form a protective oxide layer over part of the MOS gate capable of preventing corrosion and contamination during subsequent etching operations.
2. Description of Related Art
Metal-oxide-semiconductor (MOS) transistor is an important semiconductor device in an integrated circuit. The MOS transistor acts like a switch that can be switched ON or OFF through its gate. Since the gate is a major component in the operation of the MOS device, any deviation in the gate's voltage sensitivity can lead to serious control problems.
FIGS. 1A through 1C
are schematic, cross-sectional views showing the progression of manufacturing steps according to a conventional method of producing a MOS device. First, as shown in
FIG. 1A
, a gate oxide layer
12
is formed over a silicon substrate
10
. Then, a polysilicon layer
13
is deposited over the gate oxide layer
12
. Next, a barrier layer
14
is formed over the polysilicon layer
13
. The barrier layer
14
can be used to prevent the cross-diffusion of different type ions inside the polysilicon layer
13
. For example, in a dual gate MOS transistor, the P-type ions in the P-type gate and the N-type ions in the N-type gate can diffuse into each other. Thereafter, a silicide layer
15
and then a cap layer
16
are deposited in sequence over the barrier layer
14
.
Next, as shown in
FIG. 1B
, photolithographic and etching operations are conducted to pattern a gate region. Subsequently, using the cap layer
16
as a mask, a first ion implantation is carried out, implanting ions into the substrate to form lightly doped source/drain regions
17
.
Thereafter, as shown in
FIG. 1C
, spacers
18
are formed on the sidewalls of the gate. Finally, using the gate and the spacers
18
as masks, a second ion implantation is carried out implanting ions into the substrate again to form heavily doped source/drain regions
11
.
In general, the barrier layer
14
is formed using titanium material such as titanium nitride. However, titanium nitride is vulnerable to acid attack in subsequent operation whenever the gate sidewall is exposed, thereby easily contaminating manufacturing stations.
FIG. 2
is a cross-sectional view indicating the position of corrosion
19
on the sidewalls of a barrier layer in a MOS gate.
In light of the foregoing, there is a need to improve the method for manufacturing MOS gate.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method for manufacturing MOS gate capable of preventing acid corrosion and station contamination through the exposure of its barrier layer. The method includes performing a rapid thermal treatment to form a protective oxide layer over the barrier layer.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for manufacturing a MOS gate capable of preventing acid corrosion and station contamination. The manufacturing method includes the steps of sequentially forming a polysilicon layer, a barrier layer, a silicide layer and a cap layer over a silicon substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the barrier layer. Finally, the substrate is cleaned following by the formation of a source/drain region having a lightly doped drain structure on each side of the gate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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Chen Jacob
Chen Tung-Po
Huang Keh-Ching
Lin Yung-Chang
Bowers Charles
Chen Jack
Hickman Coleman & Hughes LLP
United Microelectronics Corp.
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