Patent
1996-11-13
2000-03-07
Teska, Kevin J.
39550009, G06F 1750
Patent
active
06035111&
ABSTRACT:
According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.
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Fujine Eiji
Itazu Kazushige
Kamiya Yoshihiro
Kawazoe Kazunori
Murakami Takako
Fujitsu Limited
Fujitsu VLSI Limited
Siek Vuthe
Teska Kevin J.
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