Radiation imagery chemistry: process – composition – or product th – Plural exposure steps
Reexamination Certificate
1998-03-17
2001-06-19
Huff, Mark F. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Plural exposure steps
C430S312000, C430S396000
Reexamination Certificate
active
06248508
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a circuit element, and particularly, to a method of forming a fine structure element such as a single-electron tunneling element or the like.
In recent years, integration of various circuit elements including a semiconductor device has been promoted, accompanying downsizing of circuit patterns of LSI elements forming part of a circuit element. The downsizing of patterns not only has lead to narrowed wires of elements currently used, but also has required developments of circuit elements based on a new concept, since requisites for the operational principle of the concept cannot simply be achieved by downsizing.
As a countermeasure under consideration for responding to such a demand, a single-electron tunneling element has been proposed. A single-electron tunneling element forms a fine conductive material of 0.1 &mgr;m or less which is separated by tunneling barriers and utilizes a characteristic that electrostatic energy per electron in the conductive material is sufficiently large. Therefore, it is necessary to form fine patterns with high accuracy. Particularly, in order to prepare such a single-electron tunneling element operational at a normal temperature that is effective in practical use, it is required to form a conductive material of a level of several tens nm or less. However, it is difficult for a normal lithography method to form such a fine pattern with sufficient accuracy of, e.g., ±10% or less with respect to a designed size, which is equivalent to a range of plus and minus several nm or less.
Conventionally, a processing mode of a scanning tunnel microscope (STM) is used to prepare such a fine pattern in many cases. Processing using the STM achieves only a very low throughput, and therefore, cannot be adopted in mass-production in the future. Meanwhile, it has been attempted to form a polycrystal narrow wire having a wire width of about 0.1 &mgr;m or less by using a normal electron beam lithography method, and to obtain a desired characteristic by using connections at grain boundaries of polycrystal. However, there is a limit to artificial control of grain boundaries of polycrystal within the capacity of current techniques. It is therefore difficult to ensure uniformity over the entire surface of the substrate.
Thus, downsizing of elements has been accompanied by more and more difficulties in achieving both a high throughput and high accuracy. Not only in case of a single-electron tunneling element, but also in case of forming a fine pattern with a sufficient throughput and high accuracy, there is a problem that no effective method has been established.
The present invention has been made in view of the above situation and has an object of providing a method of manufacturing a circuit element, which is capable of forming a fine pattern with a useful throughput and useful accuracy, thereby to realize a fine circuit element such as a single-electron tunneling element or the like.
BRIEF SUMMARY OF THE INVENTION
To achieve an object as described above, of the first aspect of the present invention, there is provided a method of manufacturing a circuit element, comprising: a step of performing first exposure for transferring a pattern having a narrowed portion for forming a particular pattern, onto an exposure-target substrate; and a step of moving the pattern in a direction not parallel to a segment forming an outer circumference of the narrowed portion and performing second exposure for transferring the pattern onto the exposure-target substrate.
In addition, of the second aspect of the present invention, there is provided a method of manufacturing a circuit element, comprising: a step of forming a first insulating layer on a conductive substrate, a conductive layer on the first insulating layer, and a resist formed on the conductive layer; a step of performing first exposure for transferring a pattern having a narrowed portion for forming a particular pattern, onto the resist; a step of moving the pattern in a direction not parallel to a segment forming an edge of the narrowed portion, and of performing second exposure for transferring the pattern onto the resist, thereby to form a resist pattern; and a step of selectively etching the conductive layer with the resist pattern used as a mask.
Further, of the third aspect of the present invention, there is provided a single-electron tunneling element comprising: a first conductive layer formed on a semiconductor substrate, for forming a drain electrode; a second conductive layer formed on the semiconductor substrate, for forming a source electrode; a third conductive layer formed between the first and second conductive layers; a fourth conductive layer grounded and formed on the first conductive layer, with a first insulating layer inserted therebetween; a fifth conductive layer grounded and formed on the second conductive layer, with a second insulating layer inserted therebetween; a sixth conductive layer formed on the third conductive layer, with a third insulating layer inserted therebetween; and a seventh conductive layer formed on the sixth conductive layer, with a fourth insulating layer inserted therebetween, for forming a gate electrode.
Preferred embodiments of the present invention are as follows:
(1) The exposure-target substrate includes a conductive thin film and a positive resist, and the method comprises a step in which a pattern after developing is transferred onto the conductive thin film by reactive ion etching.
(2) A material whose oxide has an insulating characteristic is used as the conductive thin film, and the method comprises an oxidation step or an isotropic etching step after the step of reactive ion etching.
(3) Si is used as the conductive thin film, and the oxidation step is a thermal oxidation step.
(4) The parallel movement of the pattern is achieved by parallel movement of a mask stage on which a mask as an exposure original is mounted.
(5) The parallel movement of the pattern is achieved by parallel movement of an exposure target substrate stage on which the exposure-target substrate is mounted.
(6) The parallel movement of the stage is achieved by a piezoelectric element connected to the stage.
(7) The parallel movement of the pattern is achieved by parallel movement of a mirror included in an optical system for exposure.
(8) The method further comprises a step of forming a contact hole, a step of filling the contact hole with a conductive material, and a step of forming a wiring layer electrically connected with the conductive material filling the contact hole.
According to the present invention, first exposure is performed with respect to a pattern having a narrowed portion for forming a particular pattern, and thereafter, the pattern is moved parallel in a direction not parallel to a segment forming the outer circumference of the narrowed portion and second exposure is performed. In this manner, a pattern finer than a limit achieved by using a conventional exposure method can be formed with a practically useful throughput and accuracy.
The present invention thus contributes to realization of a fine structure element such as a single-electron tunneling element or the like.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 5229645 (1993-07-01), Nakashima
patent: 5811222 (1998-09-01), Gardner
patent: 5837426 (1998-11-01), Tseng
patent: 3-1522 (1991-01-01), None
patent: 3-44980 (1991-02-01), None
Higurashi Hitoshi
Murooka Ken-ichi
Barreca Nicole
Huff Mark F.
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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