Manufacture of semiconductor device with copper wiring

Details Manufacture of semiconductor device with copper wiring Manufacture of semiconductor device with copper wiring

2001-03-20

2004-06-08

Nguyen, Thanh (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S676000, C438S680000

Reexamination Certificate

active

06746957

ABSTRACT:

This application is based and claims priority on Japanese Patent Application 2000-242816, filed on Aug. 10, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device with copper wiring and its manufacture method.
In this specification, wiring made of copper or copper alloy consisting essentially of copper is called copper wiring. Copper wiring is intended to be inclusive of copper wiring with a barrier layer.
b) Description of the Related Art
Demands for high integration of semiconductor integrated circuits are high. Fine circuit elements such as active elements as well as fine wiring are therefore required. For fine wiring, in place of Al conventionally used as wiring material, attention has been paid to Cu which has a lower resistance and a higher tolerance of electromigration (EM).
Cu is difficult to be worked for fine patterning. Namely, it is difficult to form a wiring line by forming a wiring layer and a mask such as resist on the wiring layer, and finely etching it, as opposed to Al wiring. In place of this method, a damascene process is performed for Cu wiring. With this process, a wiring trench is formed in an insulating layer, a Cu layer is embedded in the trench by plating or the like, and then an unnecessary Cu layer on the insulating layer is removed by chemical mechanical polishing (CMP) or the like.
In a multi-layer wiring structure, a via conductor interconnecting wiring levels is required. A single damascene process and a dual damascene process are known. With the single damascene process, a via conductor and wiring are formed by different damascene processes, and with the dual damascene process, a via conductor and wiring are formed at the same time. From the viewpoint of process simplification, the dual damascene process is more effective.
Cu has the nature that it diffuses into an insulating layer and degrades the insulation characteristics. In order to prevent Cu diffusion into an insulating layer, it is desired to form a barrier layer as an underlying layer. When a Cu layer is formed as a main wiring layer, electroplating is often used. It is desired to form a conductive seed layer for electroplating.
A barrier layer has been formed by sputtering metal nitride such as TaN and TiN. Although this barrier layer is electrically conductive, if this layer is used as a seed layer, the efficiency of electroplating cannot be made high because this layer has a high resistance. From this reason, a Cu layer formed by sputtering has been used as a seed layer.
As the degree of scaling-down proceeds, there is a tendency that the aspect ratio of a recess such as a via hole and a wiring trench becomes high. It is not easy to uniformly form a metal film through sputtering in a recess having a high aspect ration. The higher aspect ratio becomes, the more difficult it becomes to uniformly form a metal film on the side wall of a recess.
Chemical vapor deposition (CVD) is now becoming popular as a method of forming a uniform film in the recess having a high aspect ration. A barrier layer capable of being formed by CVD may be a TiN layer, a WN layer, a ZrN layer, a TaN layer of the like. Reports on CVD growth of TiN layer and ZrN layer have been given already. As a seed layer capable of being formed by CVD, A Cu layer has been reported which uses copper (1) trimethylvinylsilylhexafluoroacethylacetonato (Cu (hfac) tmve) or the like as source material.
Although it is desired to form the barrier layer and seed layer for Cu wiring by CVD, this technology has not been established yet.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a Cu wiring manufacturing method suitable for fine patterning.
It is another object of the invention to provide a semiconductor device manufacturing method in which high purity Cu wiring is formed by CVD.
It is another object of the invention to provide a semiconductor device manufacturing method in which Cu wiring having high adhesion force is formed by CVD.
It is another object of the invention to provide a semiconductor device having Cu wiring formed by CVD and being less peeled off.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: (a) preparing a semiconductor substrate formed with an insulating layer having a wiring recess; and (b) forming a conductive layer by chemical vapor deposition on a surface of the semiconductor substrate including an inner surface of the wiring recess, while lamp light is applied to the semiconductor substrate, the conductive layer consisting essentially of copper.
With this method, a Cu layer having a low impurity concentration can be formed.
A semiconductor device having high reliability Cu wiring can be formed.


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