Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Polycrystalline semiconductor
Reexamination Certificate
1997-03-24
2002-04-09
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Polycrystalline semiconductor
C438S337000, C438S366000
Reexamination Certificate
active
06368946
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of manufacturing a semiconductor device with an epitaxial semiconductor zone, whereby
a first layer of insulating material, a first layer of non-monocrystalline silicon, and a second layer of insulating material are provided in that order on a surface of a silicon wafer,
a window with a steep wall is etched through the second layer of insulating material and the first layer of non-monocrystalline silicon, so that the first layer of insulating material becomes exposed,
the wall of the window is provided with a protective layer,—the first insulating layer is selectively etched away within the window and below an edge of the first layer of non-monocrystalline silicon adjoining the window such that both the edge of the first layer of non-monocrystalline silicon itself and the surface of the wafer become exposed within the window and below said edge,
semiconductor material is selectively deposited such that the epitaxial semiconductor zone is formed on the exposed surface of the wafer, and an edge of polycrystalline semiconductor material connected to the epitaxial semiconductor zone is formed on the exposed edge of the first layer of non-monocrystalline silicon,
an insulating spacer layer is provided on the proctective layer on the wall of the window, and
a second layer of non-monocrystalline silicon is deposited.
The semiconductor device may be a bipolar transistor here while the epitaxial semiconductor zone forms the base of the transistor. The emitter of the transistor is then formed through diffusion from the second layer of non-monocrystalline silicon. The base is contacted through the first non-monocrystalline layer of silicon, the emitter through the second non-monocrystalline layer of silicon. The semiconductor device may alternatively be a MOS transistor. The MOS transistor is then formed in the epitaxial semiconductor zone. In that case, a gate oxide layer is formed on the epitaxial zone before the second layer of non-monocrystalline silicon is deposited. A pattern of conductors, from which the source and drain zones are diffused into the epitaxial zone, is then formed in the first layer of non-monocrystalline silicon before the first layer of insulating material is deposited. The source and drain are contacted by the conductors formed in the first layer of non-monocrystalline silicon. The second layer of non-monocrystalline silicon here forms the gate electrode of the MOS transistor.
It is of major importance, both in the manufacture of the bipolar transistor and in the manufacture of the MOS transistor, that during the selective deposition no semiconductor material should be deposited on the protective layer provided on the edge of the window. A layer deposited there would cause a short-circuit from the emitter to the base or from the source to the drain, as the case may be.
EP-A-0 535 350 discloses a method of the kind mentioned in the opening paragraph whereby the first layer of insulating material comprises silicon oxide, the second layer of insulating material silicon nitride, and the protective layer provided on the window wall silicon nitride. Si
1−x
Ge
x
is selectively deposited as the semiconductor material, x being greater than 0.2 and smaller than 0.4.
In practice, one or several silicon wafers are heated in a reaction chamber while a mixture of gases is conducted over the wafers in the selective deposition of semiconductor material. The deposition process is monitored by means of test data obtained in that a layer is deposited on a bare test wafer of silicon. During deposition, this test wafer is covered over its entire surface with a layer of semiconductor material. When the method is carried out, however, wafers positioned in the reaction chamber are not covered over their entire surfaces with semiconductor material during the deposition, but only on the silicon exposed within the windows present on the wafer, not on the protective layer on the window walls and not on the second layer of insulating material. The deposition process progresses completely differently within the comparatively small windows than on the test wafer which is covered with semiconductor material over its entire surface. The test data obtained from the test wafer are therefore not representative of the deposition in the windows. Since it cannot be directly measured how the process progresses within the comparatively small windows, moreover, it is very difficult to monitor the selective deposition process during the formation of the epitaxial semiconductor zone.
SUMMARY OF THE INVENTION
The invention has for its object inter alia to improve the method mentioned in the opening paragraph such that the selective deposition process during the formation of the epitaxial semiconductor zone can be monitored in a simple manner.
According to the invention, the method is for this purpose characterized in that, before the selective deposition of the semiconductor material, a top layer is provided on the second layer of insulating material, which top layer is made of a material on which non-monocrystailine semiconductor material will grow during the selective deposition of the semiconductor material.
Not only the silicon exposed within the windows present on the wafer is now covered with semiconductor material, but also the top layer provided on the second layer of insulating material on the wafers present in the reaction chamber. It is only the walls of the windows coated with the protective layer which are not provided with semiconductor material. This means that the wafers are substantially entirely covered with semiconductor material. It is found in practice that in that case the deposition can indeed be monitored by means of the test data obtained from the test wafer. It is found that a monocrystalline layer is deposited on the test wafer as quickly and to the same thickness as on the silicon exposed within the windows. It is surprisingly found that the fact that a non-monocrystalline semiconductor material is formed on the top layer instead of a monocrystalline one plays no part here.
Preferably, a top layer of non-monocrystalline silicon is provided on the second layer of insulating material. A layer of non-monocrystalline semiconductor material is then deposited thereon during the deposition of semiconductor material. After the formation of the epitaxial semiconductor zone and after the provision of the insulating spacer layer on the wall of the window, the second layer of non-monocrystalline silicon is then deposited. A connection conductor for the emitter zone is formed therein in the case of a bipolar transistor, whereas the gate electrode is formed here in the case of a MOS transistor. The same pattern may then be simply etched into the top layer of non-monocrystalline silicon, into the layer of non-monocrystalline semiconductor material deposited on the top layer, and into the second layer of non-monocrystalline silicon for the formation of the connection conductor or gate electrode. Said pattern can be etched in one and the same plasma when the semiconductor material is silicon or Si
1−x
Ge
x
with 0.1<x <0.4.
The top layer is formed on the second layer of insulating material in a simple manner when the top layer is already provided on the second layer of insulating material before etching of the window, and the window is etched also through the top layer.
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De Boer Wiebe B.
Dekker Ronald
Terpstra Doede
Timmering Cornelis E.
Gross Russell
Mulpuri Savitri
U.S. Phillips Corporation
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