Manufacturable GaAs VFET process

Details Manufacturable GaAs VFET process Manufacturable GaAs VFET process

1998-09-21

2001-10-30

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S720000, C438S742000, C438S945000

Reexamination Certificate

active

06309918

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to a process for fabricating GaAs vertical field effect transistors (VFET) and more specifically to a manufacturable GaAs VFET process.
BACKGROUND OF THE INVENTION
In the fabrication of vertical field effect transistors (VFETs) it is common to form gate areas by implanting or otherwise doping a substrate or epitaxial layer on the substrate. The doped areas or implanted areas must then be activated by a relatively high annealing temperature. The annealing temperature is high enough to cause major problems with any ohmic metal that has been previously deposited on the substrate. For example, most of the ohmic metals contain gold and annealing temperatures will cause gold to diffuse into the substrate and produce a very bad ohmic contact.
Thus, in prior art VFETs it is necessary to do all doping and annealing prior to the deposition of ohmic contacts. Any source or gate positioning must be accomplished through very careful alignment, which adds greatly to the cost and substantially reduces reliability. Further, since the deposition of metal contacts is one of the last steps to be performed, no probing of the prior art VFETs can be performed prior to completion. This again adds unduly to the cost, since early difficulties in the process cannot be detected.
It would be highly advantageous to provide a manufacturable GaAs VFET process which overcomes these drawbacks.
It is a purpose of the present invention to provide a new and improved manufacturable GaAs VFET process.
It is another purpose of the present invention to provide a new and improved manufacturable GaAs VFET process which allows the use of ohmic contacts prior to implant and activation steps.
It is still another purpose of the present invention to provide a new and improved manufacturable GaAs VFET process which allows the use of source metal as a self-aligned etch and implant mask.
It is a further purpose of the present invention to provide a new and improved manufacturable GaAs VFET process which allows testing of the VFETs at intermediate points in the process.
SUMMARY OF THE INVENTION
The above problems and others are at least partially solved and the above purposes and others are realized in a manufacturable GaAs VFET process including providing a substrate structure with a doped GaAs supporting substrate, a lightly doped first epitaxial layer including GaAs positioned on a first surface of the supporting substrate, and a heavily doped second epitaxial layer including GaAs positioned on the first epitaxial layer. A temperature tolerant conductive layer is positioned on the second epitaxial layer and patterned to define a plurality of source areas underlying the patterned portions of the conductive layer. The portions of patterned conductive layer are used as a mask and a plurality of gate trenches are etched through the second epitaxial layer and into the first epitaxial layer of the substrate structure adjacent the source areas. The bottoms of the gate trenches are spaced vertically from the second epitaxial layer. Material is implanted in the bottoms of the gate trenches to form implanted gate areas in the gate trenches and the implanted gate areas are activated by annealing. A gate contact is formed in communication with the implanted gate areas, a source contact is formed in communication with the portions of patterned conductive layer overlying the source areas, and a drain contact is formed on the rear surface of the substrate structure.


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