Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
2001-03-16
2004-10-12
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C714S047300, C327S175000
Reexamination Certificate
active
06804793
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to integrated circuits, such as microprocessors, and more particularly to a system and method for optimizing performance of integrated circuits by dynamically manipulating the clock of such integrated circuits to account for events such as power disturbances, therein.
BACKGROUND
Typically, an integrated circuit (or “chip”) utilizes a clock to control the circuits therein. As is well known in the art, chips are commonly designed such that their circuits operate synchronously according to a clock signal. That is, the exact times at which any output of the circuits can change states are determined by a clock signal. The clock signal is generally a rectangular pulse train or square wave signal input to or generated within the chip. While some chips (or portions thereof) may operate asynchronously, such asynchronous components are generally more difficult to design and troubleshoot than are synchronous components. For instance, synchronous components are generally easier to troubleshoot because the circuit outputs can change only at specific instants of time. In other words, such components of the chip are synchronized to the clock-signal transitions (also known as “clocks”) of the chip.
Because operation of the chip's circuits are triggered upon clock-signal transitions, “events” (or “power disturbances”) are often encountered upon the occurrence of particular clock-signal transitions. That is, as a chip's circuits operate they draw power, and upon a clock-signal transition occurring many of the circuits may draw additional power to perform the tasks triggered by such clock-signal transition. As a result, clock-signal transitions often result in voltage transients within the chip. Because the operation of the chip's circuits is triggered by clock-signal transitions, much of the circuits' operation is congregated at the clock-signal transitions. Therefore, power disturbances are commonly encountered upon clock-signal transitions. For instance, the power drawn by the circuits may be relatively flat (constant) until the occurrence of a particular clock-signal transition in which many of the circuits are triggered, thereby causing an increase in the power drawn by such circuits.
For example, upon the leading edge of a clock-signal transition, a program counter (e.g., a register) may be incremented. Additionally, at some point the program counter will flip all of its bits (which may, for example, be 256 bits or more) over from all ones to its beginning point of all zeros, which may cause the output of many gates within the chip to change states (e.g., change from an output of 1 to an output of 0). Such operation of many gates being triggered upon the occurrence of the clock-signal transition will typically result in a power disturbance (e.g., a very high voltage transient) within the chip. Of course, many other situations may be encountered in which a clock-signal transition may trigger operation of circuitry within the chip resulting in a power disturbance.
Additionally, certain clock-signal transitions result in higher voltage transients than other clock-signal transitions. For instance, in the above example of a program counter, the clock-signal transition in which all of the program counter's bits change their state results in a much higher voltage transient than a clock-signal transition in which only one or two of the program counter's bits change their state. Of course, the clock-signal transition resulting in the program counter changing the state of all of its bits occurs only on a relatively small percentage of the clock-signal transitions (e.g., only once out of every 65 thousand clock-signal transitions).
Thus, depending on the operations triggered within the chip on each clock-signal transition, certain clock-signal transitions result in a much greater power disturbance than others. As still another example, suppose that on 60 percent of the clock-signal transitions within a chip a 100 millivolt (mV) drop in voltage occurs within the chip, on 30 percent of the clock-signal transitions a 150 mV drop in voltage occurs within the chip, and on 10 percent of the clock-signal transitions, a 200 mV drop in voltage occurs within the chip. Prior art chips are generally implemented to operate at a frequency suitable for the absolute worst case power disturbance that may be encountered to prevent the chip from failing upon the occurrence of such worst case power disturbance. That is, during development of a chip it is typically tested with some code sequence designed to cause the absolute worst case power disturbance in the chip's performance, and from such testing a suitable clock frequency for the chip is determined that enables the chip to operate even upon the occurrence of such worst case power disturbance.
For instance, in the above example, the chip's clock signal would be implemented at a sufficiently low frequency such that the chip does not fail upon the occurrence of a 200 mV drop in voltage. That is, prior art chips are commonly designed having additional voltage margin implemented therein such that the chips are capable of performing even when the chips' operation result in voltage transients within the chips. However, the worst case power disturbance may only be encountered on a very small percentage of the clock-signal transitions (e.g., on only 10 percent of the clock-signal transitions in the above example). Thus, prior art chip designs sacrifice chip performance during those clock-signal transitions that do not trigger such worst case power disturbance (e.g., during 90 percent of the clock-signal transitions in the above example) in order to prevent failure of the chip during the clock-signal transitions that do trigger such worst case power disturbance. Of course, such a sacrifice has been deemed much more desirable in chips of the prior art than an implementation which results in failure of the chip during the worst case power disturbances. Accordingly, performance of prior art chips has been limited by the implementation of a static clock signal set at a frequency sufficiently low to enable the chip to operate during the worst case power disturbances.
SUMMARY OF THE INVENTION
The present invention is directed to a system and method which enable dynamic manipulation of a clock signal within an integrated circuit to enable optimum performance of the integrated circuit. That is, a desire exists for a system and method which enable a clock signal to be manipulated within an integrated circuit to allow for optimum performance of the chip depending on events, such as power disturbances, being (or about to be) encountered by the chip. As used herein, “events” include any situations that result in or lead to a disturbance within the integrated unit. “Disturbance” is intended to be used broadly to encompass any type of disturbance within an integrated circuit, including without limitation power disturbance and operational disturbance (e.g., incorrect performance or failure of the integrated circuit).
The present invention is directed to a system and method which provide an integrated circuit having a clock signal which it can dynamically manipulate in response to detected events. In a preferred embodiment, the integrated circuit includes synchronous circuitry that receives and operates according to a clock signal. The integrated circuit of a preferred embodiment further includes event detection circuitry that is arranged to monitor the operation of the integrated circuit and detect an event therein. Additionally, clock manipulator circuitry is included in the integrated circuit of a preferred embodiment to manipulate the clock signal, responsive to the event detection circuitry detecting an event, to enable the integrated circuit to cope with the detected event without failing.
In response to an event being detected, the clock manipulator circuitry may be implemented to manipulate the clock signal in various manners, such as by altering the duty cycle of the clock signal,
Josephson Don D
Naffziger Samuel D.
Hewlett--Packard Development Company, L.P.
Lee Thomas
Wang Albert
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