Managing VT for reduced power using power setting commands...

Electrical computers and digital processing systems: support – Computer power control

Reexamination Certificate

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Details

C713S322000

Reexamination Certificate

active

06477654

ABSTRACT:

TECHNICAL FIELD
The invention relates to integrated circuits and more particularly intelligent power management of the integrated circuit.
BACKGROUND OF INVENTION
The application and acceptance of portable electronic devices has emphasized the importance of controlling and or optimizing power consumption. Actually controlling power consumption may be satisfied by adjusting the body voltage (i.e. the voltage magnitude between body and source) applied to transistors in an integrated circuit (IC). By increasing the body to source voltage, transistors achieve a higher threshold voltage, consume less power but, on the other hand, provide lower performance and vice versa. It is also known that the IC can be broken down into several partitions or sectors and the body voltage controlled on a partition by partition basis, see in this regard copending application entitled “Low Powering Apparatus for Automatic Reduction of Power in Active and Standby Modes” by Dean et al filed Jul. 21, 1998, Ser. No. 09/120,211, ultimately issued as U.S. Pat. No. 6,011,383, and “Device and Method to Reduce Power Consumption in Integrated Semiconductor Devices Using a Lower Power Groggy Mode”, Bertin et al, filed on Sep. 24, 1998, Ser. No. 09/159,861, ultimately issued as U.S. Pat. No. 6,097,243, and “ASIC Low Power Activity Detector to Change Threshold Voltage”, Dean et al, U.S. Ser. No. 09/159,898, filed on Sep. 24, 1998, and ultimately issued as U.S. Pat. No. 6,097,241. The disclosures of these applications are incorporated herein by reference.
Notwithstanding the foregoing, the art lacks a technology to allow optimizing power management in light of the actual repertoire of instructions applied to a partitioned integrated circuit.
SUMMARY OF INVENTION
The present invention provides an integrated circuit in which power is managed intelligently relative to the demands placed on the integrated circuit. In order to implement the foregoing the integrated circuit is designed with discrete functional units, each dedicated to a particular function or functions where each of the functional units has an independently controllable body voltage or threshold voltage (V
t
). Consequently, each of the functional units can be operated at one of plural power levels depending on the body or threshold voltage applied thereto and independent of other functional units. Since the functional units have discrete functions, it is possible to correlate specific software instructions with one or a set of functional units. Execution of the instruction at a high rate will require the correlated functional units to be in a high power state, other functional units, i.e. those not correlated with the instruction, need not be in the high power state.
For example, assume the IC had functional units dedicated to floating point arithmetic functions and a modem operation and the application program or program segment being executed involved a remote file transfer but no floating point operations. One could optimize the performance, that is reduce power consumption but maximize speed of the IC, by reducing the power consumed by the floating point arithmetic functional unit(s) to a minimum and raising the power consumption of the modem-related unit(s). The raising of the power level in the modem-related units is justified by the increase in performance while the power savings on the floating point arithmetic functional unit(s) is obtained at no cost since the absence of floating point arithmetic operations means the performance of that functional unit or units is of no consequence to the execution of the application or program segment.
In general it is an object of the invention to control the power consumption of various functional units so as to present functional units in a high power state when instructions requiring their operation are to be executed and concomitantly to minimize power wasted on functional units which are not involved in current instructions. This may be effected by powering up a functional unit which is called on and powering down that unit thereafter.
In connection with one embodiment of the invention, an application, i.e. a series of instructions to be executed, is recompiled or modified so as to add to the application one or more power control instructions. The power control instructions each may be addressed so as to indicate to which of the functional unit or units that power control instruction applies. The intent is that the power control instructions, after being added to the instruction stream, are stored along with the preexisting instructions so that when the program containing the instructions is executed, the power control instructions will optimize the power status of the plural functional units. More particularly, the functional units which are required for execution of a particular instruction should be in an appropriate power state, that is a high power state at the time the instruction will be executed. Other functional units, which are not required for execution of the particular instruction, need not be in a high power state. In order to add the appropriate power control instructions, an analysis function analyzes the instructions contained in the application to identify correlated functional units. The analysis unit will assume that on initialization all functional units will be in their lowest power state.
The analysis function identifies the population of functional units and related parameters, such as the time required to transition the unit from a low to a higher power state. Thereafter the analysis function correlates the instructions in the user application or program with the various functional units. With the result of this correlation the analysis function can determine which functional units are required to be in a higher power state for each of the instructions in the application. Then the analysis function selects a unit and, for each unit performs the following.
First, a determination is made regarding whether it is possible to determine which code segment(s) in the application exclusively use the unit, where a code segment is defined to have one and only entrance and exit. If such code segment(s) can be identified, then we can be assured that the instruction sequence which eventuates in use of the unit is known. This is in contrast to more complex instruction sequencing as in the case of branch operations. Where exclusive use of the unit can be determined the analysis function can insert a power up and power down instruction, addressed to the unit being processed in a location of the instruction sequence to bracket the segment. That is the power up instruction is placed at the entrance to the segment and a power down instruction is placed at the termination of the segment. If on the other hand it is not possible to determine one or more code segment which exclusively uses the unit then it is necessary to determine if the unit is ever used in the application. If the unit is never used then it can remain in a low power state and it is placed on an always off list. If the unit is ever used, then it is placed on an always on list.
After each unit is processed in this way, there are two terminal functions that are necessary. In a first of the terminal functions, a power down power control instruction is placed in the beginning of the application and addressed to each unit on the always off list and a power up power control instruction is placed in the beginning of the application and addressed to each always on unit. In the second of the terminal instructions a power down power control instruction is placed at the end of the application and addressed to each unit in the IC.
By appropriately inserting the power control instructions in the ordered sequence of instructions of the application as described, a modified ordered list or sequence of instructions is produced by the analysis function. This modified ordered list is then stored so that the integrated circuit can later execute the instructions of the modified ordered list when they are extracted from storage.
Accordingly, the inventi

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