Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-07-12
2011-07-12
Kim, Hong (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C712S220000, C712S225000, C712S240000, C711S135000, C711S137000, C711S144000, C711S145000, C711S151000, C711S156000, C711S158000, C711S159000, C711S165000, C718S103000
Reexamination Certificate
active
07979642
ABSTRACT:
A data processing apparatus is provided comprising processing circuitry for executing multiple program threads. At least one storage unit is shared between the multiple program threads and comprises multiple entries, each entry for storing a storage item either associated with a high priority program thread or a lower priority program thread. A history storage for retaining a history field for each of a plurality of blocks of the storage unit is also provided. On detection of a high priority storage item being evicted from the storage unit as a result of allocation to that entry of a lower priority storage item, the history field for the block containing that entry is populated with an indication of the evicted high priority storage item. When later a high priority storage item is allocated to a selected entry of the storage unit, a comparison operation between the allocated high priority storage item and the indication in the history field for the block containing the selected entry is carried out, and on detection of a match condition a lock indication associated with that entry is set to inhibit further eviction of that high priority storage item.
REFERENCES:
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patent: 2008/0263341 (2008-10-01), Ozer et al.
patent: 2008/0295105 (2008-11-01), Ozer et al.
S. E, Raasch et al, “Applications of Thread Prioritization in SMT Processors” Proceedings of Multithreaded Execution, Architecture and Compilation Workshop, Jan. 1999, pp. 1-9.
G. K. Dorai et al, “Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance” Proceedings of the 11thAnnual International Conference on Parallel Architectures and Compilation Techniques, Sep. 2002.
Bull David Michael
Özer Emre
ARM Limited
Kim Hong
Nixon & Vanderhye P.C.
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