Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-04-04
2006-04-04
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S133000, C711S134000, C711S135000, C711S141000, C711S144000, C711S146000, C707S793000
Reexamination Certificate
active
07024521
ABSTRACT:
Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is associated with each cache coherence controller identifying memory lines associated with the local cluster that are cached in remote clusters. Techniques are provided for managing eviction of entries in the cache coherence directory by locking memory lines in a home cluster without causing a memory controller to generate probes to processors in the home cluster.
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HyperTransport ™ I/O Link Specification Revision 1.03, HyperTransport ™ Consortium, Oct. 10, 2001, Copyright © 2001 HyperTransport Technology Consortium.
Beyer Weaver & Thomas LLP
Newisys, INC
Sparks Donald
Truong Bao Q
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