Managing processing delays in an isochronous system

Details Managing processing delays in an isochronous system Managing processing delays in an isochronous system

2007-09-28

2011-10-25

Dudek, Jr., Edward J (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S154000, C711SE12022, C711SE12103, C710S015000

Reexamination Certificate

active

08046524

ABSTRACT:
Command cycles incorporate mechanisms to inform a host processor in advance of a need to service the memory so that the host can respond when it suits the host, but in time for the service to be performed before a catastrophic failure. The regular host cycle need not be interrupted for such notification.

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