Managing power on integrated circuits using power islands

Details Managing power on integrated circuits using power islands Managing power on integrated circuits using power islands

2006-05-23

2006-05-23

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07051306

ABSTRACT:
Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands where power consumption is independently controlled within each of the power islands. A power manager determines a target power level for one of the power islands. The power manager then determines an action to change a consumption power level of the one of the power islands to the target power level. The power manager performs the action to change the consumption power level of the one of the power islands to the target power level.

REFERENCES:
patent: 6462976 (2002-10-01), Olejniczak et al.
patent: 6598148 (2003-07-01), Moore et al.
patent: 6631502 (2003-10-01), Buffet et al.
patent: 6667648 (2003-12-01), Stout et al.
patent: 6779163 (2004-08-01), Bednar et al.
patent: 6820240 (2004-11-01), Bednar et al.
Lackey et al. “Managing Power and Performance for System-on-Chip Design using Voltage Islands”, Nov. 2002, IEEE International Conference on Computer Aided Design, pp. 195-202.
“Sloving the Power Management Dilemma in System-On-Chip Asic Design”, Apr. 2002, IBM Technology Group.
Semeraro et al., “Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture”, Nov. 2002, IEEE 35thAnnual International Symposium on Microarchitecture, Proceddings pp. 356-367.
Akui et al., “Dynamic Voltage and Frequency Management for Low-Power Embedded Microprocessor”, Feb. 2004, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, vol. 1, pp. 64-513.
Talpes et al., “Toward a Multiple Clocl/Voltage Island Design Style for Power-Aware Processors”, May 2005, IEEE Transactions on Very Large Scale Integration (VLSI) system, vol. 13, iss. 5, pp. 591-603.
U.S. Appl. No. 10/996,739, Randy J. Caplan, Systems and Methods for Minimizing Static Leakage of an Integrated Circuit, Nov. 24, 2004.
Gupta, R., et al., “Low Power Wireless Networked System Design,” HotChips, Aug. 18, 2002, Stanford, CA.
Tsai, Y-F et al., “Implications of Technology Scaling on Leakage Reduction Techniques,” DAC 2003, Jun. 2-6, 2003, ACM, Anaheim, CA, USA.
Li L. et al., “Managing Leakage Energy in Cache Hierarchies,” Journal of Instruction-Level Parallelism, 2003, pp. 1-24, vol. 5.
Hu, J.S. et al., “Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch,” Proc. of IEEECS Annual Symposium on VLSI (ISVLSI 2003), Feb. 20-21, 2003, Tampa, FL.
Zhang, W. et al., “Compiler Support for Reducing Leakage Energy Consumption,” Proceedings of the 6th Design Automation and Test in Europe Conference (DATE-03), Mar., 2003, Munich, Germany.
Degalahal, V. et al., “Analyzing Soft Errors in Leakage Optimized SRAM Design,” Proceedings of the 16th International Conference on VLSI Design, Jan. 2003, New Delhi, India.
Li, L. et al., “Leakage Energy Management in Cache Hierarchies,” 11th International Conference on Parallel Architectures and Compilation Techniques (PACT'02), Sep. 2002.
Duarte, D. et al., “Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes,” Proceedings of the 20th International Conference on Computer Design (ICCD), Sep. 16-18, 2002, Freiberg, Germany.
Duarte, D. et al., “Impact of Technology Scaling and Packaging on Dynamic Voltage Scaling Techniques,” Proceedings of the 15th Annual IEEE International ASIC/SOC Conference, Sep. 25-28, 2002, Rochester, NY.
Kim, S et al. “Predictive Precharging for Bitline Leakage Energy Reduction,” Proceedings of 15th Annual IEEE International ASIC/SOC Conference, Sep. 25-28, 2002, Rochester, NY.
Ramanarayanan, R. et al. “Characterizing Dynamic and Leakage Power Behavior in Flip Flops,” Proceedings of the 15th Annual IEEE International ASIC/SOC Conference, Sep. 2002.
Chen, G. et al. “Adaptive Garbage Collection for Battery-Operated Environments,” Proceedings of USENIX JVM02 Symposium, Aug. 2002.
Chen, G. et al. “Energy Savings Through Compression in Embedded JavaEnvironments,” Proceedings of the CODES'02, Jun. 2002.
Delaluz, V. et al. “Hardware and Software Techniques for Controlling DRAM Power Modes,” IEEE Transaction on Computers, Nov. 2001, vol. 50.
Delaluz, V. et al. “Scheduler-Based DRAM Energy Management,” DAC 2002, Jun. 10-14, 2002, New Orleans, LA, USA, ACM.
Kim, S. et al. “Partitioned Instruction Cache Architecture for Energy Efficiency” ACM Transactions on Computational Logic, Jul. 2002, pp 1-23, vol. V, No. N.
De La Luz, V. et al. “Automatic Data Migration for Reducting Energy Consumption in Multi-Bank Memory Systems,” DAC 2002, Jun. 10-14, 2002, New Orleans, LA, USA.
Duarte, D. et al. “Impact of Technology Scaling in the Clock System Power,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI, Apr. 25-26, 2002, Pittsburgh, PA.
Duarte, D. et al. “A Complete Phase-Locked Loop Power Consumption Model,” Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02), 2002, IEEE.
Duarte, D. et al. “Evaluating Run-Time Techniques for Leakage Power Reduction,” Proceedings of the 15th International Conference on VLSI Design (VLSID'02) 2002, IEEE.
Zhang, W. “Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction,” Proceedings of the 34th Annual International Symposium on Microarchitecture (MICRO'01), Dec. 2001.
Kim, S. et al. “Energy Efficient Instruction Cache Using Page-Based Placement,” Proceedings of International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'01, Nov. 1-17, 2001, Atlanta, GA, USA.
Hezavei, J. et al. “Input Sensitive High-Level Power Analysis,” Proceedings of the 2001 IEEE Workshop on Signal Processing Systems (SiPS), Sep. 2001, pp. 149-156.
Kim, S. et al. “Power-aware Partitioned Cache Architectures,” Proceedings of ACM/IEEE International Symposium on Low Power Electronics and Design, 2001, ILSPED'01, Aug. 6-7, 2001, Huntington Beach, CA.
Delaluz, V. “DRAM Energy Management Using Software and Hardware Directed Power Mode Control,” Proceedings of the 7th International Symposium on High Performance Computer Architecture, Jan. 20-24,, 2001, Monterrey, Mexico.
De Micheli, G. et al. “System-Level Power Optimization: Techniques and Tools,” DATE 2000.
Manne, S. et al. “Cool Chips Tutorial,” 32nd Annual International Symposium on Micorarchitecture, Nov. 15, 1999, Haifa, Israel.
Filseth, E. “Tally Power into Cost of ‘Free’ Silicon,” EETimes, Jan. 11, 1999, located at http://www.eetimes.com/story/speakout/OEG19990111S028.
Frenkil, J. “A Multi-Level Approach to Low-Power IC Design,” IEEE Spectrum, Feb. 1998, Vo. 35, No. 2.
“Managing Power in Ultra Deep Submicron ASIC/IC Design,” May 2002, Synopsys, Inc.
Pangrle, B. “Low Power Design: A Holistic Approach in an Era of New Semiconductor Technologies,” San Diego Telecom Council Semiconductor SIG, Nov. 14, 2002.
Rabaey, J. “Design Aids for Low Power: Part II Architecture and System Levels,” 1997.
Grunwald, D. et al. “Kool Chips Workshop,” MICRO33, Dec. 10, 2000, Monterey, CA.
Flynn, J. et al., “Power Management in Complex SoC Design,” Synopsys, Apr. 2004, located at http://www.synopsys.com/sps.
Halter et al., “A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS Circuits”, in Proc. IEEE Custom Integrated Circuits Conf., 1997, pp. 475-478.
Horiguchi et al., “Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-Scale LSI's”, IEEE Journal of Solid-State Circuits, Nov. 1993, vol. 28, No. 11.
Kao et al., “Dual-Threshold Voltage Techniques for Low-Power Digital Circuits”, IEEE Journal of Solid-State Circu

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