Managing multiprocessor operations

Details Managing multiprocessor operations Managing multiprocessor operations

2004-11-30

2008-08-26

Elmore, Reba I (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S146000, C711S152000, C711S163000

Reexamination Certificate

active

07418557

ABSTRACT:
In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.

REFERENCES:
patent: 6314526 (2001-11-01), Arendt et al.
patent: 6467050 (2002-10-01), Keung
patent: 6615373 (2003-09-01), Elko et al.
patent: 6622260 (2003-09-01), Marisetty et al.
patent: 6751705 (2004-06-01), Solomon et al.
patent: 6772298 (2004-08-01), Khare et al.
B.M. Ozaki, et al., “Software Fault Tolerance in Architectures with Hierarchical Protection Levels”, IEEE, Aug. 1988, pp. 31-43.
Y. Tamir, et al., “Application-Transparent Process-Level Error Recovery for Multicomputers”, IEEE, 1989, pp. 296-305.
L.M. Silva et al., “Global Checkpointing for Distributed Programs”, IEEE, 1992, pp. 155-162.
IBM Corp., “Dynamically Structured Messaging Mechanism”, Research Disclosure, Apr. 2001, pp. 681-686.
D.J. Sorin, et al., “SafetyNet: Improving with Availability of Shared Memory Multiprocessors with Global Checkpoint/ Recovery”, IEEE, 2002, pp. 123-134.

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