Managing latencies in accessing memory of computer systems

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

Reexamination Certificate

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Details

C718S100000, C711S113000

Reexamination Certificate

active

06944736

ABSTRACT:
The present invention, in various embodiments, provides techniques for managing latencies in accessing memory of computer systems. In one embodiment, upon accessing the memory system for a piece of data used by a first process, a latency manager determines the access time to acquire the piece of data in the memory system. The latency manager then compares the determined access time to a threshold. If the determined access time is greater than the threshold, the latency manager triggers an interrupt for the operating system to switch threads or processes so that execution of the first process is postponed and execution of a second process starts. Various embodiments include the latency manager is polled for the access time when the processor is stalled, the latency manager triggers a process switch when a particular memory subsystem is accessed, etc.

REFERENCES:
patent: 5297265 (1994-03-01), Frank et al.
patent: 5784582 (1998-07-01), Hughes
patent: 6049867 (2000-04-01), Eickemeyer et al.
patent: 6233599 (2001-05-01), Nation et al.
patent: 6418510 (2002-07-01), Lamberts
patent: 6697935 (2004-02-01), Borkenhagen et al.

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