Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
1999-06-21
2002-12-03
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S400000, C713S600000, C710S061000, C712S245000
Reexamination Certificate
active
06490689
ABSTRACT:
TECHNICAL FIELD
This invention relates, in general, to timing facilities within a computing environment and, in particular, to employing physical clocks that have been expanded to enhance timing precision.
BACKGROUND ART
Typically, processors of a computing environment either include or have access to timing facilities that provide date and time of day information. In the ESA/390 architecture offered by International Business Machines Corporation, the timing facilities include a time-of-day (TOD) clock, which provides a high-resolution measure of real-time suitable for the indication of the date and time.
In one example, the time-of-day clock is represented as a 64-bit-integer value that is set and incremented in an architecturally prescribed fashion based on real-time. This basic TOD clock is set to a value that corresponds to present time in Coordinated Universal Time (UTC), where bit
51
is updated once per microsecond and a clock value of zero corresponds to Jan. 1, 1900, 0 a.m.
The TOD-clock facility of ESA/390 is based on various architectural requirements, which are summarized below:
1. Uniqueness: Two executions of a STORE CLOCK instruction (used by a program to obtain the date and/or time), possibly on different central processing units (CPUs), are to store different values. Programs are to be able to rely on this uniqueness rule to produce unique identifiers for new object instances.
2. Monotonicity: The values stored by two STORE CLOCK instructions correctly imply the sequence of execution of the two instructions; namely, the instruction that occurs later in time stores a larger time value. This is true whether the two instructions are executed on the same or different CPUs. Programs are to be able to rely on this monotonicity rule to determine the sequence of occurrence of distinct events.
3. Predictable resolution: The resolution of the TOD clock is such that the incrementing rate is comparable to the instruction execution rate of the machine and should advance at least once during a time equal to, for instance, 10 average instructions. Performance characteristics of program loops can be determined by comparing time values at the beginning and end of the program. A predictable resolution allows these performance algorithms to be independent of the processor speeds.
Although efforts have been made to meet the above requirements, technological enhancements in processors have and continue to place strain on the ability to meet those requirements, as well as other requirements or features. Thus, enhanced timing facilities are needed to better meet the current requirements, as well as the requirements or desires of the future. For example, enhanced timing facilities are needed that employ expanded physical clocks, which are faster and continue to meet the uniqueness requirement.
SUMMARY OF THE INVENTION
The shortcomings of the prior art are overcome and additional advantages are provided through the provision of a method of employing expanded physical clocks. The method includes, for instance, beginning execution of an instruction that places a value of a physical clock in a physical clock field of a clock representation, the physical clock field being unable to accommodate the value provided by the physical clock, and wherein the value encroaches upon at least a portion of another predefined field of the clock representation; and delaying completion of the instruction, wherein the value is accommodated in the clock representation and a correct value is provided for the another predefined field.
In one embodiment of the invention, the delaying includes delaying completion of the instruction until at least a portion of the value encroaching upon the another predefined field includes a correct value for an encroached portion of the another predefined field.
In another aspect of the present invention, a method of employing enhanced physical clocks is provided. The method includes, for example, expanding a physical clock to provide enhanced precision of the physical clock; and delaying completion of an instruction that uses the physical clock to preserve behavior of the instruction even though the physical clock has expanded.
In yet another aspect of the present invention, a system of employing expanded physical clock is provided. The system includes, for instance, means for beginning execution of an instruction that places a value of a physical clock in a physical clock field of a clock representation, the physical clock field being unable to accommodate the value provided by the physical clock, wherein the value encroaches upon at least a portion of another predefined field of the clock representation; and means for delaying completion of the instruction, wherein the value is accommodated in the clock representation and a correct value is provided for the another predefined field.
In another aspect of the present invention, a system of employing enhanced physical clocks is provided. The system includes, for example, means for expanding a physical clock to provide enhanced precision of the physical clock; and means for delaying completion of an instruction that uses the physical clock to preserve behavior of the instruction even though the physical clock has expanded.
In a further aspect of the present invention, a system of employing expanded physical clocks is provided. The system includes, for instance, a processor adapted to begin execution of an instruction that places a value of a physical clock in a physical clock field of a clock representation, the physical clock field being unable to accommodate the value provided by the physical clock, wherein the value encroaches upon at least a portion of another predefined field of the clock representation; and the processor being further adapted to delay completion of the instruction, wherein the value is accommodated in the clock representation and a correct value is provided for the another predefined field.
In another aspect of the present invention, an article of manufacture including at least one computer usable medium having computer readable program code means embodied therein for causing the employing of expanded physical clocks is provided. The computer readable program code means in the article of manufacture, includes, for instance, computer readable program code means for causing a computer to begin execution of an instruction that places a value of a physical clock in a physical clock field of a clock representation, the physical clock field being unable to accommodate the value provided by the physical clock, wherein the value encroaches upon at least a portion of another predefined field of the clock representation; and computer readable program code means for causing a computer to delay completion of the instruction, wherein the value is accommodated in the clock representation and a correct value is provided for the another predefined field.
In yet another aspect of the present invention, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform a method of employing enhanced physical clocks is provided. The method includes, for instance, expanding a physical clock to provide enhanced precision of the physical clock; and delaying completion of an instruction that uses the physical clock to preserve behavior of the instruction even though the physical clock has expanded.
Advantageously, the present invention provides a mechanism for employing expanded physical clocks. An instruction, which has not been updated for the expansion, can nevertheless use an expanded clock. In particular, the instruction is delayed in orders accommodate the expanded clock.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.
REFERENCES:
patent: 4050096 (1977-09-01), Bennett et al.
patent: 4841524 (1989-06-01), Miyaou et al.
patent: 5133077 (1992-07-01), Karne et a
Elko David Arlen
Nick Jeffrey M.
Smith, Sr. Ronald M.
Webb Charles F.
Ehrlich, Esq. Marc A.
Gaffin Jeffrey
Gonzalez, Esq. Floyd A.
Heslin Rothernberg Farley & Mesiti P.C.
Mai Rijue
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