Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-01-16
2007-01-16
Elmore, Stephen C. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S138000, C711S144000, C711S145000, C711S154000
Reexamination Certificate
active
10805105
ABSTRACT:
Provided are a method, system, and program for managing Input/Output (I/O) requests in a cache memory system. A request is received to data at a memory address in a first memory device, wherein data in the first memory device is cached in a second memory device. A determination is made as to whether to fetch the requested data from the first memory device to cache in the second memory device in response to determining that the requested data is not in the second memory device. The requested data in the first memory device is accessed and the second memory device is bypassed to execute the request in response to determining not to fetch the requested data from the first memory device to cache in the second memory device.
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Choubal Ashish V.
Foulds Christopher T.
Gumma Madhu R.
Le Quang T.
Elmore Stephen C.
Intel Corporation
Konrad Raynes & Victor LLP
Victor Davis W.
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