Managing formal verification complexity of designs with...

Details Managing formal verification complexity of designs with... Managing formal verification complexity of designs with...

2004-07-29

2008-08-26

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C715S252000

Reexamination Certificate

active

07418678

ABSTRACT:
A counter abstraction tool generates an abstraction model for one or more counters in a circuit design for use with a formal verification system. The tool detects the presence of a counter in a circuit design, identifies one or more special values for the counter, and creates an abstraction for the counter. The tool can automatically perform the abstraction, guide a user in configuring the appropriate abstraction for the counter, or perform a combination of automatic and manual abstraction. The tool may further accommodate related counters.

REFERENCES:
patent: 2002/0095645 (2002-07-01), Rodeh
patent: 2003/0200515 (2003-10-01), Ly et al.
patent: 2004/0123254 (2004-06-01), Geist et al.
patent: 2004/0153308 (2004-08-01), McMillan et al.
patent: 2004/0168137 (2004-08-01), Baumgartner et al.

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