Managing and supporting multithreaded resources for native...

Electrical computers and digital processing systems: virtual mac – Task management or control

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C712S242000

Reexamination Certificate

active

08087018

ABSTRACT:
A computer implemented method and apparatus to manage multithread resources in a multiple instruction set architectures environment comprising initializing a first thread from a first context. The initialization of the first thread is suspended at a position in response to an operating system request call to create the first thread. A second thread from a host environment is created based on the position. After the second thread is created, completion of the initialization of the first thread based on the position is then performed. Other embodiments are described in the claims.

REFERENCES:
patent: 2003/0126313 (2003-07-01), Kerly
patent: 2005/0071841 (2005-03-01), Hoflehner et al.
patent: 2005/0120194 (2005-06-01), Kissell
patent: 2006/0184920 (2006-08-01), Wang et al.
Chen et al., “Java JNI Bridge: A Framework for Mixed Native ISA Execution”, IEEE, Mar. 26-Mar. 29, 2006, pp. 1-11.
Venstermans et al., “64-bit versus 32-bit Virtual Machines for Java”, Software, Practice, and Experience, Sep. 15, 2005, pp. 1-26.
PCT Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration for PCT Counterpart Application No. PCT/CN2006/000580, 9 pages (Jan. 11, 2007).
“Instruction Set Architecture (ISA)”, http://kmh.ync.ac.kr/PcNcMicro/student2.html, 5 pages, (Jul. 8, 2001).
“Instruction Set Architecture (ISA)”, http://shekel.jct.ac.il/˜citron/ca/isa.html, 4 pages, (Aug. 8, 2002).
Joseph D. Wieber, Jr., et al., “Introduction to Intrinsics”, http://www.intel.com/cd/ids/developer/asmo-na/eng/59644.htm?prn=Y, 3 pages, (Jan. 26, 2006).
“Intel Extended Memory 64 Technology”, http://www.intel.com/technology/64bitextensions/, 2 pages, (Jun. 8, 2004).
“Preparing Code for the IA-64 Architecture (Code Clean)—A Programmer's Reference”, Intel Corporation, 36 pages, (2000).
Cristina Cifuentes, et al., “Walkabout—A Retargetable Dynamic Binary Translation Framework”, Sun Microsystems, Inc., 33 pages, (Jan. 2002).
“Thread (computer science)”, http://en.wikipedia.org/wiki/Multithreading, 8 pages, (Mar. 21, 2002).
“Instruction Set”, http://en.wikipedia.org/wiki/Instruction—set, 4 pages, (Apr. 5, 2002).
Leonid Baraz, et al., “IA-32 Execution Layer: A two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems”, Intel Corporation, 11 pages, (Sep. 25, 2003).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Managing and supporting multithreaded resources for native... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Managing and supporting multithreaded resources for native..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Managing and supporting multithreaded resources for native... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4312680

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.