Management of microcode lock in a shared computing resource

Details Management of microcode lock in a shared computing resource Management of microcode lock in a shared computing resource

2004-10-05

2008-03-25

McCarthy, Christopher (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C718S104000

Reexamination Certificate

active

07350117

ABSTRACT:
In a power controller or other computing resource shared by multiple processors, an ID is written to the lock register, thereby designating a master processor. A timer is then initialized to count for a predetermined period. Periodically, the master processor transmits a “heartbeat” signal to the shared resource, indicating that its operation remains normal. Upon receipt of the heartbeat signal, the timer is reset and begins a new count for the predetermined period. If the timer reaches the end of the period without having received a heartbeat signal, indicating that the master processor has failed or hung, the lock register is cleared again and an interrupt signal is broadcast to all of the processors. The processors compete for master status anew and, when an ID is successfully written to the lock register, the timer is restarted and the new master periodically transmits its heartbeat signal.

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